Secure digital input/output interface (SDIO)
RM0090
1066/1731
DocID018909 Rev 11
31.9.15 SDIO
data
FIFO
register (SDIO_FIFO)
Address offset: 0x80
Reset value: 0x0000 0000
The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs
contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store
multiple operands to read from/write to the FIFO.
31.9.16 SDIO
register
map
The following table summarizes the SDIO registers.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
FIF0Data
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
bits 31:0
FIFOData:
Receive and transmit FIFO data
The FIFO data occupies 32 entries of 32-bit words, from address:
SDIO base + 0x080 to SDIO base + 0xFC.
Table 180. SDIO register map
Offset
Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x00
SDIO_POWER
Reser
ve
d
PWRCTRL
0x04
SDIO_CLKCR
Re
se
rv
e
d
HWFC_E
N
NEGE
D
G
E
WIDBUS
BY
P
ASS
PW
R
S
A
V
C
LKEN
CLKDIV
0x08
SDIO_ARG
CMDARG
0x0C
SDIO_CMD
Reser
ve
d
CE-A
TA
CMD
nIE
N
ENCMDcompl
S
D
IO
Suspen
d
CPS
M
EN
WA
IT
P
E
N
D
W
A
IT
INT
WA
IT
R
E
S
P
CMD
INDEX
0x10
SDIO_RESPCMD
Reserved
RESPCMD
0x14
SDIO_RESP1
CARDSTATUS1
0x18
SDIO_RESP2
CARDSTATUS2
0x1C
SDIO_RESP3
CARDSTATUS3
0x20
SDIO_RESP4
CARDSTATUS4
0x24
SDIO_DTIMER
DATATIME
0x28
SDIO_DLEN
Reserved
DATALENGTH
0x2C
SDIO_DCTRL
Re
se
rv
ed
SD
IO
E
N
RW
M
O
D
RW
S
T
O
P
RW
S
TA
R
T
DBL
O
CKSIZE
DMA
E
N
DT
M
O
D
E
DTDIR
DT
E
N
0x30
SDIO_DCOUNT
Reserved
DATACOUNT