Advanced-control timers (TIM1&TIM8)
RM0090
528/1731
DocID018909 Rev 11
Figure 110. External trigger input block
For example, to configure the upcounter to count each 2 rising edges on ETR, use the
following procedure:
1.
As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.
2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR
register
4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
5. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal.
Figure 111. Control circuit in external clock mode 2
17.3.5 Capture/compare
channels
Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
give an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
ETR
0
1
TIMx_SMCR
ETP
divider
/1, /2, /4, /8
ETPS[1:0]
ETRP
filter
ETF[3:0]
downcounter
f
DTS
TIMx_SMCR
TIMx_SMCR
ETR pin
CK_INT
encoder
mode
external clock
mode 1
external clock
mode 2
internal clock
mode
ETRF
TRGI
TI1F
TI2F or
or
or
(internal clock)
CK_PSC
ECE
TIMx_SMCR
SMS[2:0]
Counter clock = CK_CNT = CK_PSC
Counter register
35
36
34
ETR
CNT_EN
f
CK_INT
ETRP
ETRF