3.2.4 Ramped Input Switching
When switching between input clocks that are not frequency locked to each other, ramped input switching should be enabled to ensure
a smooth frequency transition on the outputs. In this situation, it is also advisable to enable phase buildout, as discussed in the previous
section to minimize the input-to-output clock skew after the frequency ramp has completed.
When ramped clock switching is enabled, the Si5386 will enter into holdover and then exit from holdover when the exit ramp has
been calculated. Note that it can take up to ~1 second for the Si5386 to make the ramp calculations. This means that ramped
switching behaves like an exit from holdover. This is particularly important when switching between two input clocks that are not the
same frequency so that the transition between the two frequencies will be smooth and linear. Ramped switching is not needed for
cases where the input clocks are locked to the same upstream clock source. The CBPro 'DSPLL Configure' page defaults to enable
'Ramped Exit from Holdover', but the user needs to select the 'Ramped Input Switching & Exit from Holdover' option when switching
between non-synchronized input clocks.The same ramp rate settings are used for both exit from holdover and clock switching. For
more information on ramped exit from holdover including the ramp rate, see Section
Table 3.6. Ramped Switching Decision Matrix
Frequency Difference be-
tween Input Frequencies
f
Pfd
> 500 kHz
f
Pfd
< 500 kHz
Zero PPM
Select "Ramped Exit from Holdover"
Non-Zero PPM
If difference is:
• Less than 10 ppm, select "Ramped Exit from Hold-
over".
• More than 10 ppm, select "Ramped input switching
and Ramped Exit from Holdover".
Select "Ramped input switching and Ramped
Exit from Holdover".
Table 3.7. Ramped Input Switching Control Registers
Setting Name
Hex Address
[Bit Field]
Function
RAMP_STEP_INTERVAL
0x052C[7:5]
Calculated by CBPro based on the selected ramp rate.
RAMP_STEP_SIZE
0x05A5[2:0]
Calculated by CBPro based on the selected ramp rate.
RAMP_SWITCH_EN
0x05A6[3]
Enable frequency ramping on an input switch.
HSW_MODE
0x053A[1:0]
Input switching mode select.
3.2.5 Hitless Switching, Loss of Lock (LOL), and Fastlock
When doing a clock switch between clock inputs that are frequency locked, LOL may be momentarily asserted. In such cases, the
assertion of LOL will invoke Fastlock. Because Fastlock temporarily increases the loop BW by asynchronously inserting new filter
parameters into the DSPLL’s closed loop, there may be a small transient at the clock outputs when Fastlock is entered or exited. For
this reason, it is suggested that automatic entry into Fastlock be disabled by writing a zero to FASTLOCK_AUTO_EN whenever a clock
switch might occur.
3.2.6 Glitchless Input Switching
The DSPLL has the ability to switch between two input clock frequencies that are up to ±20 ppm apart. The DSPLL will pull-in to the
new frequency at a rate determined by the DSPLL loop bandwidth. The DSPLL loop bandwidth is set using registers 0x0508–0x050D.
Note that if “Fastlock” is enabled then the DSPLL will pull-in to the new frequency using the Fastlock Loop Bandwidth. Depending on
the LOL configuration settings, the loss of lock (LOL) indicator may assert while the DSPLL is pulling-in to the new clock frequency.
Outputs will never generate runt pulses during input clock transitions.
Si5386 Rev. E Reference Manual • Clock Inputs
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
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Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 9, 2021
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