3.2.2 Use Case Scenario: Using More Than Two Inputs
When a DSPLL uses more than two inputs there is a rare but small chance that if two of the inputs are lost at the exact same time
(within 1 PFD clock period), the switch to the 3rd available input will not occur correctly, and the state machine will be stuck pointing to a
lost clock causing the PLL to lose lock. It won’t recover unless manually switched to an available input.
Workaround: For designs using more than two inputs with hitless switching enabled follow the guidance below:
1. Do not disable two inputs at the exact same time. If both inputs must be shut off, then leave at least one clock period of delay
between shutting off one input and then shut off the other input.
2. Also consider including a LOS ISR (Interrupt Service Routine) that always checks for a LOS event with the active input pointing to
an input that is LOS.
Outside the ISR make sure the device is already configured for input register control mode if this is an available feature for the device.
Set IN_SEL_REGCTRL[0] = 1 for devices that have the option of both pin or register control.
LOS Interrupt Service Routine Pseudocode Example:
Step 1. If the interrupt pin/bit is set– read and store the LOS flags LOS_FLG 0x0012[3:0]. If any of the
LOS_FLG bits are set, then proceed to step 2. Otherwise, exit this ISR.
Step 2. Read the Input Active Register (IN_ACTV[3:0] 0x0507[3:0]) to know which input clocks are active.
Compare this to the LOS flags asserted in step 1. This comparison will reveal if the PLL input is set to an
input that does not have a clock present (i.e., LOS=1).
Step 3. If the input points to a LOS input, then set the input switch to manual mode.
Set CLK_SWITCH_MODE[1:0] = 0
Step 4. Change the input to an available active input.
Set IN_SEL[2:1] Set to 0, 1, 2 or 3, whichever is the available active input.
Step 5. Verify IN_ACTV to make sure the input is pointing to the active input as expected.
Step 6. Go back to automatic mode.
Set CLK_SWITCH_MODE[1:0] = 1 for Automatic non-revertive, or 2 for automatic revertive.
For further guidance and workarounds, contact
.
3.2.3 Hitless Input Switching with Phase Buildout
Phase buildout, also referred to as hitless switching, prevents a phase change from propagating to the output when switching between
two clock inputs with an integer related frequency and a fixed phase relationship (i.e., they are phase/frequency locked, but with a
non-zero phase difference). When phase buildout is enabled, the DSPLL absorbs the phase difference between the two input clocks
during a clock switch. When phase buildout is disabled, the phase difference between the two inputs is propagated to the output at a
rate determined by the DSPLL loop bandwidth. Lower PLL loop bandwidth provides more filtering.
Hitless Switching with Phase Buildout should be used for applications where the input clocks are all locked to a common upstream
clock, as in most synchronization systems. Gapped clocks are not supported.
Table 3.5. Hitless Switching Enable Bit
Register Name
Hex Address
[Bit Field]
Function
HSW_EN
0x0536[2]
Hitless switching is enabled = 1, or disabled = 0.
Si5386 Rev. E Reference Manual • Clock Inputs
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
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Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 9, 2021
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