Non-standard CMOS refers to a signal with a swing of (1.8V, 2.5 V or 3.3 V) +/-5% that has been attenuated/level-shifted in order to
comply with the specified non-standard maximum VIL and minimum VIH specifications. Please refer to the data sheet for the VIL and
VIH specifications. For non-compliant inputs, a resistive attenuator is required as shown. It is not recommended to add the attenuation
circuit for compliant inputs as it adversely affects the signal integrity at the input pins. Note that maximum input frequency cannot be
guaranteed with the attenuator circuit. If an input exceeds 3.3 V +5% then the input must be attenuated before going into the chip.
The pulsed CMOS input format allows pulse-based inputs, such as frame-sync and other synchronization signals having a duty cycle
much less than 50%. These pulsed CMOS signals are dc-coupled and use the “Pulsed CMOS” Input Buffer selection. The resistor
divider values given in the diagram will work with up to 1 MHz pulsed inputs. Pulsed CMOS refers to a low-frequency (up to 1 MHz),
low/high duty cycle signal with a swing of (1.8 V, 2.5 V or 3.3 V) +/-5% that has been attenuated/level-shifted in order to comply with the
specified non-standard maximum VIL and minimum VIH specifications. Refer to the data sheet for the VIL and VIH specifications. Make
sure to not violate the max and min specifications or use the attenuator circuit to ensure the specifications.
Input clock buffers are enabled by setting the IN_EN 0x0949[3:0] bits appropriately for IN3 through IN0. Unused clock inputs may be
powered down and left unconnected at the system level. For standard mode inputs, both input pins must be properly connected, as
shown in the above figure, including the “Standard AC-Coupled Single Ended” case. In any of the CMOS modes, it is not necessary to
connect the inverting INx input pin.
To place the input buffer into any one of the CMOS modes, the corresponding bit must be set in IN_PULSED_CMOS_EN 0x0949[7:4].
Make sure the corresponding input bit is set to 1 for DC-Coupled CMOS Mode. Although the name is IN_PULSED_CMOS_EN this
setting actually corresponds to enable all DC-coupled CMOS modes. IN_CMOS_USE1P8 0x094F[7:4] determines Standard CMOS
mode when the input bit is high and Non-Standard or Pulsed CMOS Mode when the input bit is low. The difference between Standard
CMOS and Non-Standard/ Pulsed CMOS is the VIL/VIH settings, which should be reviewed carefully from the data sheet.
Table 3.4. Input Clock Control and Configuration Registers
Setting Name
Hex Address [Bit Field]
Function
Si5386
IN_EN
0949[3:0]
Enable each of the input clock buffers for IN3
through IN0.
IN_PULSED_CMOS_EN
0949[7:4]
Enable CMOS mode for each input
1 = DC-Coupled CMOS Mode either Standard
or Non-Standard/Pulsed CMOS
0 = Standard AC-Coupled Mode
7: IN3
6: IN2
5: IN1
4: IN0
IN_CMOS_USE1P8
094F[7:4]
1 = Standard DC-Coupled CMOS mode
0 = Non-Standard or Pulsed DC-Coupled
CMOS Mode
7: IN3
6: IN2
5: IN1
4: IN0
Review data sheet for max and min VIL/VIH
thresholds
3.2.1 Unused Inputs
Unused inputs can be disabled and left unconnected when not in use. Register 0x0949[3:0] defaults the input clocks to being enabled.
Clearing the unused input bits will disable them. For inputs that are enabled but have an inactive clock source, a weak pullup or
pulldown resistor may be added to minimize noise pickup.
Si5386 Rev. E Reference Manual • Clock Inputs
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
21
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 9, 2021
21
