2.1.2 NVM Programming
The NVM is two-time writable by the user. Once a new configuration has been written to NVM, the old configuration is no longer
accessible.
While polling DEVICE_READY during the procedure below, the following conditions must be met in order to ensure that the correct
values are written into the NVM:
• VDD and VDDA power must both be stable throughout the process.
• No additional registers may be written during the polling. This includes the page register at address 0x01. DEVICE_READY is
available on every register page, so no page change is needed to read it.
• Only the DEVICE_READY register (0xFE) should be read during this time.
The procedure for writing registers into NVM is as follows:
1. Write all registers as needed. Verify device operation before writing registers to NVM.
2. You may write to the user scratch space (registers 0x026B to 0x0272) to identify the contents of the NVM bank.
3. Write 0xC7 to NVM_WRITE register.
4. Poll DEVICE_READY until DEVICE_READY=0x0F.
5. Set NVM_READ_BANK 0x00E4[0]=1.
6. Poll DEVICE_READY until DEVICE_READY=0x0F.
Alternatively, Steps 5 and 6 can be replaced with a Hard Reset, either by RSTb pin, HARD_RST register bit, or power cycling the
device to generate a POR. All of these actions will load the new NVM contents back into the device registers.
Note that the I2C_ADDR setting in register 0x000B is not saved as part of this NVM write procedure. To update this register in a
non-volatile way, the "Si534x8x I2C Address Burn Tool" allows updating this value one time. This utility is included in the ClockBuilder
Pro installation and can be accessed under the "Misc" folder in the installation directory.
Table 2.2. NVM Programming Registers
Register Name
Hex Address
[Bit Field]
Function
ACTIVE_NVM_BANK
0x00E2[7:0]
Identifies the active NVM bank.
NVM_WRITE
0x00E3[7:0]
Initiates an NVM write when written with value 0xC7.
NVM_READ_BANK
0x00E4[0]
Download register values with content stored in NVM.
DEVICE_READY
0x00FE[7:0]
Indicates that the device is ready to accept com-
mands when value = 0x0F.
2.2 Free Run Mode
Once power is applied to and initialization is complete the DSPLL will automatically enter Free run mode, generating the output
frequencies determined by the NVM. The frequency accuracy of the generated output clocks in Free run mode is entirely dependent
on the frequency accuracy of the XAXB reference clock. Any temperature drift of this frequency will be tracked at the output clock
frequencies. A TCXO or OCXO is recommended for applications that need better frequency accuracy and lower wander while in Free
run or Holdover modes. Since there is little jitter attenuation from the XAXB pins to the clock outputs, devices should use a low-jitter
XAXB reference clock to minimize output clock jitter.
2.3 Lock Acquisition Mode
The device monitors all inputs for a valid clock. If a valid clock is available for synchronization, the DSPLL will automatically start the
lock acquisition process. If the Fastlock feature is enabled, the DSPLL will acquire lock using the Fastlock Loop Bandwidth setting and
then transition to the DSPLL Loop Bandwidth setting when lock acquisition is complete. During lock acquisition the outputs will generate
a clock that follows the VCO frequency change as it pulls-in to the input clock frequency.
2.4 Locked Mode
Once locked, the DSPLL will generate output clocks that are both frequency and phase locked to its selected input clock. At this point,
the XAXB reference clock frequency drift does not affect the output frequency. A loss of lock pin (LOLb) and status bit indicate when
lock is achieved. See section
for more details on the operation of the loss of lock circuit.
Si5386 Rev. E Reference Manual • Modes of Operation
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
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Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 9, 2021
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