Sharp JX-8200, Руководство по обслуживанию

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Pin Name
Pull Up/
Pull Dn
(1)
Type Description
PIO[5]/DCD I/O Programmable Input/Output or Data Carrier Detect: As input, it can be alternatively used as
Data Carrier Detect for external modem or as a programmable I/O pin. In the modem option a
change on the pin will set a flag in the Modem Status register and cause an interrupt.
NOTE: This pin behaves as DCD when bit-6 of the PIO Control Register is 1, and as PIO[4]
when bit-6 is 0.
DSR I Data Set Ready: Used to start the receiving of data on RXD. A change in the value of this input
will set a flag in the Modem Status register and cause an interrupt.
RXD I Serial Data Input: Data input to the receiver.
DTR O Data Terminal Ready: A LOW indicates that the part is ready to receive data. This output is
controlled by the data written into the Modem Control register.
TXD O Serial Data Output: Data from the transmit register is shifted out via this pin.
Misc.
TEST P.D.
(R3710 only)
I Master Output Enable: When TEST is HIGH and RESET
∗
is active, ALL the device outputs
and I/O are tri-stated (in a system, TEST should be pulled down to GND).
RESET
∗
I Reset: Will reset the R3710 or R3740 to the initial state.
VDD +5V (+/–5%)
VSS Ground
NOTE: (1) Pull Up/Pull Dn identifies pins with internal Pull Up (P.U.) or Pull Down (P.D.) resistors. The R3740 has internal P.U. resistors only for
input pins, and no internal P.D. resistors. P.U./P.D. values are: For R3710, 35K-150Kohm depending on the process variation, and for
R3740, 30Kohm maximum.
d.
Parallel I/F controller (79R3741/41A P1284
ENHANCEMENT ASIC)
I. FEATURES
(Centronics Interface)
•
provides full compliance for IEEE 1284 ECP, Nibble, and Byte
modes
•
eliminates requirement for external LS244 buffers for Centronics
Status signals
•
provides complete Host Timeout support based on the IEEE 1284
specification
•
ensures proper completion of all termination events
•
detects all Initialization pulses during Compatibility mode and
notifies CPU via interrupt
•
allows direct entry into Host Busy Data Available phase directly
from negotiation to support Hosts which poll peripheral data
•
provides device identification support for all supported IEEE 1284
modes
•
indicates interface is not ready upon system powerup until
software initialization is complete
(System Interface)
•
simple 8 bit I/O interface connects directly to R3710/40 8 bit I/O
interface
•
on board register provides status and control information
•
three 8 bit registers provide programmable timing signals for any
system frequency up to 33 MHz
•
requires 2 address lines, 1 chip select for the 8 bit I/O channel, and
1 interrupt line
•
used in conjunction with the R3710/40 Centronics interface
II. Signal list (Pin arrangement)
(PINOUT TABLE)
Pin
#
Signal Name I/O
1 SYSRESET
∗
I
2 nACK I
3 Vcc
4 IOCS
∗
I
5 IOA2 I
6 IOWR
∗
I
7 nAUTOFD I
8 IOA3 I/O
9 nSTROBE I
10 Vss (GND)
-11 PERROR I
12 nINIT I
13 BUSY I
14 pld_PERROR O
15 Vcc
16 IOD7 I/O
17 SELECT I
18 IORD I
19 pld_nINIT O
20 nFAULT I
21 nSELECTIN I
22 Vss (GND) I
Pin
#
Signal Name I/O
23 Vcc
24 IOD3 I/O
25 IOD4 I/O
26 IOD5 I/O
27 IOD2 I/O
28 IOD1 I/O
29 IOD0 I/O
30 Vss (GND)
31 INTERRUPT
∗
O
32 N/C
33 pld_nSTROBE O
34 pld_SELECT O
35 Vcc
36 pld_SELECTIN O
37 pld_nFAULT O
38 pld_nACK O
39 pld_nAUTOFD O
40 pld_BUSY O
41 IOD6 I/O
42 Vss (GND)
43 SYSCLK
∗
I
44 N/C
SHARP SERVICE MANUAL JX8200SM [13] ELECTRICAL SECTION
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