Sharp JX-8200, Руководство по обслуживанию

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b. Laser printer system controller (ASIC) (IDT79R3710)
I.
Specifications
■
Pin-Compatible System Controller with Laser Printer-control
function for the IDT R30xx family of processors
■
DRAM Controller
•
1 – 40 MB direct, 1 – 3 banks direct
•
Device supported: 256K – 4M
•
Non-interleave
■
ROM Controller
•
1 – 20MB, Address-space support bank size: 1 – 8MB
•
Support for standard and burst ROMs
•
Support for interleave or non-interleave
■
Direct Interface to Adobe Typhoon rasterizer coprocessor
■
I/O Bus follows 8/16-bit Intel 80186 style
■
I/O Controller
•
Two 8-bit and two 16-bit external channels
•
DMA and non-DMA access for the 8-bit channels
•
8-32 packing, 32-8 unpacking logic for DMA access
•
16-32 packing, 32-16 unpacking for CPU/Typhoon coprocessor
accesses
•
Round robin arbitration
•
Programmable timing for I/O and control signals
•
Big and little endian support
■
PCMCIA Support
•
Through 16-bit I/O bus, using simple glue logic
•
16-bit to 32-bit packing and 32-bit to 16-bit unpacking
•
Big and little endian support
•
256MB address space dedicated to 2 PCMCIA slots
■
Engine Control
•
Supports control and status lines to the engine
•
Horizontal and vertical margin counters
■
24-bit Timer/Counter, In-Circuit testing capability
■
CPU Interface
•
33MHz for 79R3710
•
25MHz for 79R3740
■
Video Controller
•
Four-entry (32-bit wide) FIFO with data serializer
•
Video data Phase Lock Loop (PLL)
•
DMA support (with chaining)
•
Full duplex printing support
•
Inverse video
•
Video Clock is 10MHz with PLL, 85% of CPU Clock with exter-
nal clock
■
Centronics Interface
•
Bi-directional Centronics, compliant with IEEE1284
•
Supports DMA and CPU controlled transfers
•
Supports the following modes:
•
Compatible; Nibble; Byte; ECP; EPP
■
Interrupt Controller
•
6 external level interrupts (through the PIO pins)
•
14 internal interrupts
•
Individual interrupt mask capability, enabling polling or interrupt-
driven systems
■
General Purpose I/O
•
Six programmable Input (interrupts) or Output pins
■
High-performance CMOS technology
II. Block Diagram
III. Signal list (Pin configurations)
(Pin configurations)
DRAM
Control
ROM
Control
Typhoo
Coprocessor
Conteol
6
Interrupt
Controller
Timer/
Counter
PIO
System
Arbiter
CPU
Interface
CPU
Memory
System
Typhoo
Coprocessor
IDT79R3710
Engine
Interface
Video
FIFO
VIU PLL
Arbiter
BIU
FIFO
3 Ch
a
nn
el
DM
A
IO Ports
Bidirectional
Centronics
Centronics
Interface
ROMCS*[2-0]
ROMOE*
LINESYNC*
PAGESYNC*
VCLKIIN
VDATA
OEMAD
R(PIO[4])
DCD(PIO[5])
DSR
RXD
DTR
TXD
TEST
RESET*
VDD
VSS
SYSCLK*
ESTROBE*
EOE*
CSELECT
CFAULT*
CACK*
CWOE*
CPERROR
CAUTOFD*
CROE*
CWSTROBE
CBUSY
CRSTROBE
CSTROBE*
CINIT*
CSELECTIN*
PIO(5-0)
IO
D
A
T
A
(15-
0)
A
D
(31-
0)
A
DDR(
3
-2
)
B
URS
T
*
AL
E
RD*
WR
*
AC
K*
RDC
E
N
*
BU
SR
EQ
*
BU
SG
N
T
*
D
A
T
AEN
*
TA
D
O
E
*
TA
D
D
IR
*
TD
TA
C
K
*
TD
S
*
TB
R
E
Q*
TB
GN
T*
TA
S
*
TC
S
*
T
A
AC
K*
TA
T
O
E
*
D
M
AR
EQ
(1
-0
)
IOC
S
(1
-0
)*
IO
G
P
C
S
(1
-0
)*
IO
B
E
(1-
0)
*
IOA
1
IOR
D
*
IOW
R
*
DM
A
A
CK
(1
-0
)*
IOWA
IT
*
DW
R
*
C
A
S
(3-
0)
*
R
AS(2
-0
)*
DA
DR(
1
0
-0
)
ROM
VIDEO
Buffer Control
UART
3740
only
Miscellaneous
IN
T*
CPU Interface Typhoon Interface
PIO
Engine Control
Bidirectional
Centronics
I/O Bus DRAM
Note : TDS* is an I/O pin on the 3740, but only an output pin on the 3710.
SHARP SERVICE MANUAL JX8200SM [13] ELECTRICAL SECTION
13 – 6