![Samsung S3C2501X Скачать руководство пользователя страница 83](http://html.mh-extra.com/html/samsung/s3c2501x/s3c2501x_user-manual_340828083.webp)
PROGRAMMER
′′
S MODEL
S3C2501X
2-24
2.16.1.4 Register 2: Instruction and data cacheable registers
This location provides access to two registers which contain the cacheable attributes for each of eight memory
areas. The two registers provide individual control for the I and D address spaces. The opcode_2 field determines
whether the instruction-or data-cacheable attributes are programmed:
If the opcode_2 field = 0, the data-cacheable bits are programmed. For example:
MCR p15,0,Rd,c2,c0,0; Write data-cacheable bits
MRC p15,0,Rd,c2,c0,0; Read data-cacheable bits
If the opcode_2 field = 1 the instruction-cacheable bits are programmed. For example:
MCR p15,0,Rd,c2,c0,1; Write instruction cacheable bits
MRC p15,0,Rd,c2,c0,1; Read instruction cacheable bits
The format for the data and instruction cacheable bits is similar, as shown in Table2-10. Setting a bit makes an
area cacheable, clearing it makes it non-cacheable.
All defined bits in the cacheable registers are set to zero at reset.
Table 2-10. Cacheable Register Format
Register Bits
Functions
7
Cacheable bit (C_7) for area 7
6
Cacheable bit (C_6) for area 6
5
Cacheable bit (C_5) for area 5
4
Cacheable bit (C_4) for area 4
3
Cacheable bit (C_3) for area 3
2
Cacheable bit (C_2) for area 2
1
Cacheable bit (C_1) for area 1
0
Cacheable bit (C_0) for area 0
Содержание S3C2501X
Страница 1: ...S3C2501X 32 BIT RISC MICROPROCESSOR USER S MANUAL Revision 1 查询S3C2501X供应商 捷多邦 专业PCB打样工厂 24小时加急出货 ...
Страница 18: ......
Страница 275: ...MEMORY CONTROLLER S3C2501X 5 60 NOTES ...
Страница 289: ...I2C CONTROLLER S3C2501X 6 14 NOTES ...
Страница 373: ...GDMA CONTROLLER S3C2501X 9 24 NOTES ...
Страница 435: ...I O PORTS S3C2501X 12 12 NOTES ...
Страница 463: ...ELECTRICAL DATA S3C2501X 15 6 NOTES ...