Samsung S3C2501X, Руководство пользователя

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PRODUCT OVERVIEW S3C2501X
1-12
1.6 SIGNAL DESCRIPTION
Table 1-1. S3C2501X Signal Descriptions
Group Pin Name Pin Type Pad Type Description
System
Config
(20)
XCLK 1 I Phic S3C2501X PLL Clock Source. If CLKSEL is
Low, PLL output clock is used as the system
clock. If CLKSEL is high, XCLK is used as the
system clock.
HCLKO 1 O phbst24 System clock output. The internal system
clock is monitored via HCLKO. If SDRAM is
used, this clock should be used SDRAM clock.
CLKSEL 1 I Phic Clock Select for CPU PLL and system PLL.
If CLKSEL is low, CPU PLL clock is used as
ARM940T source clock and system PLL clock
is used system clock source, depending on
CLKMOD[1:0]. If CLKSEL is high, XCLK is
used both clock sources.
BUS_FILTER 1 I poar50_abb PLL filter pin for System PLL.
If the PLL is used, 320pF capacitor should be
connected between the pin and ground.
PHY_FREQ 1 I Phic PHY clock frequency select for PHY PLL.
0 = 20MHz, 1 = 25MHz
PHY_CLKSEL 1 I Phic Clock Select for PHY PLL
If this pin is set to low, the PHY PLL generates
clock depending on PHY_FREQ state. The
PHY PLL goes into power down mode with
PHY_CLKSEL set to high.
PHY_FILTER 1 O poar50_abb PLL filter pin for PHY PLL.
If the PLL is used, 320pF capacitor should be
connected between the pin and ground.
PHY_CLKO 1 O phob8 PHY clock Out
PHY PLL clock output can be monitored by
PHY_CLKO. This clock is used as the external
phy source clock.
CPU_FILTER 1 O poar50_abb PLL filter pin for System PLL.
If the PLL is used, 320pF capacitor should be
connected between the pin and ground.