Samsung S3C2501X, Руководство пользователя

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SYSTEM CONFIGURATION S3C2501X
4-20
4.8.4 PERIPHERAL CLOCK DISABLE REGISTER (PCLKDIS)
There is a peripheral clock disable register in system configuration. You can set this register with the specific
value for the purpose of power save. If you set PCLKDIS[0] to “1”, the clock for GDMA channel 0 is
disabled. Similarly, you control the clock input of each peripheral.
Register Address R/W Description Reset Value
PCLKDIS 0xF000000C R/W Peripheral clock disable register 0x0F000500
PCLKDIS Bit Description Initial State
SRreq [31] SDRAM Self-refresh request 0x0
SRack [30] SDRAM Self-refresh acknowledge ( Read only) 0x0
Reserved [29:28] Reserved for future use 0x0
Reserved [27] Reserved 1
Reserved [26] Reserved 1
Reserved [25] Reserved 1
Reserved [24] Reserved 1
SDRAMC [23] SDRAMC clock disable 0x0
MEMCON [22] MEMCON clock disable 0x0
DES [21] DES clock disable 0x0
IIC [20] IIC Clock disable 0x0
IOPC [19] IOPC clock disable 0x0
WDT [18] Watch dog timer clock disable 0x0
TIMER5 [17] TIMER5 clock disable 0x0
TIMER4 [16] TIMER4 clock disable 0x0
TIMER3 [15] TIMER3 clock disable 0x0
TIMER2 [14] TIMER2 clock disable 0x0
TIMER1 [13] TIMER1 clock disable 0x0
TIMER0 [12] TIMER0 clock disable 0x0
HUART [11] HUART clock disable 0x0
Reserved [10] Reserved 1
CUART [9] CUART clock disable 0x0
Reserved [8] Reserved 1
ETHERC1 [7] ETHERC1 clock disable 0x0
ETHERC0 [6] ETHERC0 clock disable 0x0
GDMA5 [5] GDMA channel 5 clock disable 0x0
GDMA4 [4] GDMA channel 4 clock disable 0x0
GDMA3 [3] GDMA channel 3 clock disable 0x0
GDMA2 [2] GDMA channel 2 clock disable 0x0
GDMA1 [1] GDMA channel 1 clock disable 0x0
GDMA0 [0] GDMA channel 0 clock disable 0x0