Samsung S3C2501X, Руководство пользователя

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S3C2501X MEMORY CONTROLLER
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5.7.5 EXTERNAL DATA BUS WIDTH
The SDRAM controller supports not only 32 bit data bus, but also 16 bit data bus. External data bus width can be
selected by the XW field of CFGREG.
5.7.6 MERGING WRITE BUFFER
A merging write buffer compacts the writes of all widths into quad-word, which can be efficiently transferred to
the SDRAM. The merging write buffer improves the data bandwidth of write operation. The merging write buffer
is comprised of write buffer 0 and write buffer 1. Each write buffer holds a quad word, which is the size of the
default SDRAM data burst length. Two write buffer configuration allows a new quad word to be buffered while the
contents of the other quad-word buffer are transferred to memory. These write buffers can also merge non-
contiguous writes to the same quad word address.
The conditions of the write buffer flush are as follows:
•
Write miss: there is a write to a SDRAM address outside the current merging quad word address
•
Read hit: there is a read from the same address as the merging quad word.
•
Write buffer time out: the write buffer timer reaches zero.
•
The write buffer is disabled.
When a read hit, the write-back operation is completed before the requested data is read from memory to
maintain data consistency between the write buffer and SDRAM memory.
5.7.7 SELF REFRESH
The SDRAM controller provides the auto refresh (REF) and self refresh (SREF) command to sustain the contents
of the SDRAM. The auto refresh is issued to SDRAM periodically when refresh timer is expired. The self refresh
is entered and exited by request of on-chip power manager. The self refresh is the preferred refresh mode for
data retention and low power operation of SDRAM. In self refresh mode the SDRAM ignores all the input signals
except CKE. The refresh addressing and timing are internally generated to reduced power consumption.
Before disabling clock of the SDRAM controller the SDRAM must be in self refresh mode to sustain the SDRAM
memory data. Self refresh mode might be entered or exited by asserting or deasserting the self refresh request
bit (SRreg) of the peripheral clock disable register (PLCKDIS).
It is possible to know if the SDRAM is in self refresh mode or not by reading out the SRreg bit SRack bit of the
PCLKDIS register.
If the self refresh mode change is on processing, the SRack bit of the PCLKDIS is deasserted, and if the self
refresh mode, change is completed, the SRack bit is asserted.
To recover from the self refresh mode to normal operation mode, the SRack bit shoul be checked asserted
before access the SDRAM.