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280
Timer and Counter Instructions
Section 3-6
When decrementing, the Completion Flag will be turned ON when the PV is
decremented from 0 up to the SV and it will be turned OFF again when the PV
is decremented from the SV to SV
–
1.
Flags
Precautions
Counter numbers are shared by the CNT, CNTX(546), CNTR(012),
CNTRX(548), CNTW(814), and CNTWX(818) instructions. If two counters
share the same counter number but are not used simultaneously, a duplica-
tion error will be generated when the program is checked but the counters will
operate normally. Counters which share the same counter number will not
operate properly if they are used simultaneously.
The PV will not be changed if the increment and decrement inputs both go
from OFF to ON at the same time. When the reset input is ON, the PV will be
reset to 0 and both count inputs will be ignored.
The Completion Flag will be ON only when the PV has been incremented
from the SV to 0 or decremented from 0 to the SV; it will be OFF in all other
cases.
When inputting the CNTR(012)/CNTRX(548) instruction with mnemonics, first
enter the increment input (II), then the decrement input (DI), the reset input
(R), and finally the CNTR(012)/CNTRX(548) instruction. When entering with
the ladder diagrams, first input the increment input (II), then the CNTR(012)/
CNTRX(548) instruction, the decrement input (DI), and finally the reset input
(R).
Examples
Basic Operation of CNTR(012)/CNTRX(548)
The counter PV is reset to 0 by turning the reset input (CIO 000002) ON and
OFF. The PV is incremented by 1 each time that the increment input
(CIO 000000) goes from OFF to ON. When the PV is incremented from the
SV (3), it is automatically reset to 0 and the Completion Flag is turned ON.
Likewise, the PV is decremented by 1 each time that the decrement input
(CIO 000001) goes from OFF to ON. When the PV is decremented from 0, it
is automatically set to the SV (3) and the Completion Flag is turned ON.
SV
+1
Counter PV
Completion Flag
SV
−
1
Counter PV
Completion Flag
Name
Label
Operation
Error Flag
ER
ON if N is indirectly addressed through an Index Register
but the address in the Index Register is not the PV
address of a counter.
ON if in BCD mode and S does not contain BCD data.
OFF in all other cases.
Содержание SYSMAC CS Series
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Страница 186: ...146 List of Instructions by Function Code Section 2 4 ...
Страница 194: ...154 3 35 4 MOVE BIT MOVBC 568 1273 3 35 5 BIT COUNTER BCNTC 621 1275 3 35 6 GET VARIABLE ID GETID 286 1277 ...
Страница 1320: ...1280 Model Conversion Instructions Unit Ver 3 0 or Later Section 3 35 ...
Страница 1390: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2 ...
Страница 1391: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits ...
Страница 1392: ...1352 ASCII Code Table Appendix A ...
Страница 1404: ...1364 Revision History ...