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166
Sequence Input Instructions
Section 3-3
Operand Specifications
Description
AND is used for a normally open bit connected in series. AND cannot be
directly connected to the bus bar, and cannot be used at the beginning of a
logic block. If there is no immediate refreshing specification, the specified bit
in I/O memory is read. If there is an immediate refreshing specification, the
status of the Basic Input Unit’s input terminal is read.
Flags
There are no flags affected by this instruction.
Precautions
Differentiate up (@) or differentiate down (%) can be specified for AND. If dif-
ferentiate up (@) is specified, the execution condition is turned ON for one
cycle only after the status of the operand bit goes from OFF to ON. If differen-
tiate down (%) is specified, the execution condition is turned ON for one cycle
only after the status of the operand bit goes from ON to OFF.
Immediate refreshing (!) can be specified for AND. An immediate refresh
instruction updates the status of the input bit just before the instruction is exe-
cuted from the Basic Input Unit (but not Basic Input Units on Slave Racks or
for C200H Group 2 Multi-point Input Units).
For AND, it is possible to combine immediate refreshing and up or down differ-
entiation (!@ or !%). If either of these is specified, the input is refreshed from
the Basic Input Unit just before the instruction is executed and the execution
condition is turned ON for one cycle only after the status goes from OFF to
ON, or from ON to OFF.
AND cannot be used for addresses in the DM and EM Areas. Use AND
TST(350) instead.
Area
AND bit operand
CIO Area
CIO 000000 to CIO 614315
Work Area
W00000 to W51115
Holding Bit Area
H00000 to H51115
Auxiliary Bit Area
A00000 to A95915
Timer Area
T0000 to T4095
Counter Area
C0000 to C4095
Task Flag Area
TK0000 to TK0031
Condition Flags
ER, CY, N, OF, UF, >, =, <, >=, <>, <=, ON, OFF, AER
Clock Pulses
0.02 s, 0.1 s, 0.2 s, 1 s, 1 min
TR Area
---
DM Area
---
EM Area without bank
---
EM Area with bank
---
Indirect DM/EM
addresses in binary
---
Indirect DM/EM
addresses in BCD
---
Constants
---
Data Registers
---
Index Registers
---
Indirect addressing
using Index Registers
,IR0 to ,IR15
–2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15
Содержание SYSMAC CS Series
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Страница 4: ...iv ...
Страница 30: ...xxx ...
Страница 186: ...146 List of Instructions by Function Code Section 2 4 ...
Страница 194: ...154 3 35 4 MOVE BIT MOVBC 568 1273 3 35 5 BIT COUNTER BCNTC 621 1275 3 35 6 GET VARIABLE ID GETID 286 1277 ...
Страница 1320: ...1280 Model Conversion Instructions Unit Ver 3 0 or Later Section 3 35 ...
Страница 1390: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2 ...
Страница 1391: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits ...
Страница 1392: ...1352 ASCII Code Table Appendix A ...
Страница 1404: ...1364 Revision History ...