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864
High-speed Counter/Pulse Output Instructions
Section 3-21
long time are being used; it can also cause errors in timers (TIM and TIMH)
and data tracing. Be particularly careful when the scheduled time interval
units are set to 0.5 ms or 1 ms in the PLC Setup.
Interrupts are accepted even while one instruction is being executed. There-
fore, if an interrupt is accepted while an instruction requiring a long processing
time is being executed, correct processing results may not be obtained
because both the interrupt task and the instruction may access the same
data. In such a case, use DI(693) and EI(694) to disable and enable the inter-
rupt.
3-21 High-speed Counter/Pulse Output Instructions
This section describes instructions used to control the high-speed counters
and pulse outputs.
3-21-1 MODE CONTROL: INI(880) (CJ1M-CPU21/22/23 Only)
Purpose
INI(880) can be used to execute the following operations for built-in I/O of
CJ1M CPU Units:
• To start comparison with the high-speed counter comparison table
• To stop comparison with the high-speed counter comparison table
• To change the PV of the high-speed counter.
• To change the PV of interrupt inputs in counter mode.
Interrupts
disabled
Interrupt
during
execution
Interrupt task
Instruction
Mnemonic
Function
code
Page
MODE CONTROL
INI
880
864
HIGH-SPEED COUNTER PV READ
PRV
881
868
COUNTER FREQUENCY CONVERT
PRV2
881
874
REGISTER COMPARISON TABLE
CTBL
882
878
SPEED OUTPUT
SPED
885
882
SET PULSES
PULS
886
887
PULSE OUTPUT
PLS2
887
890
ACCELERATION CONTROL
ACC
888
896
ORIGIN SEARCH
ORG
889
903
PULSE WITH VARIABLE DUTY FACTOR
PWM
891
906
Содержание SYSMAC CS Series
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Страница 186: ...146 List of Instructions by Function Code Section 2 4 ...
Страница 194: ...154 3 35 4 MOVE BIT MOVBC 568 1273 3 35 5 BIT COUNTER BCNTC 621 1275 3 35 6 GET VARIABLE ID GETID 286 1277 ...
Страница 1320: ...1280 Model Conversion Instructions Unit Ver 3 0 or Later Section 3 35 ...
Страница 1390: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2 ...
Страница 1391: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits ...
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