The Receive Buffer Overflow indicates that an overflow condition in the RX
Buffer has occurred. It is generated when the RX Buffer is full, an additional
read transfer attempts to write into the RX Buffer and the QSPI_RSER[RBOIE]
bit is set.
The AHB Buffer Overflow indicates that an overflow condition in the AHB
Buffer has occurred. It is generated when the AHB Buffer is full, an additional
read transfer attempts to write into the AHB Buffer and the
QSPI_RSER[ABOIE] bit is set.
The data from the transfers that generated the individual overflow conditions is
ignored.
• Serial Flash Command Error Interrupt Request
If the IPAEF, IPIEF flags in the QSPI_FR are set, and the related interrupt enable
bits in the QSPI_RSER are also set, then an interrupt is requested.
• Transaction Finished Interrupt Request
The IP Command Transaction Finished IRQ indicates the completion of the current
IP Command.It is triggered by the QSPI_FR[TFF] flag and is masked by the
QSPI_RSER[TFIE] bit.
33.7.2.11 TX Buffer Operation
The TX Buffer provides the data used for page programming. For proper operation it is
required to provide at least four entry in the TX Buffer prior to starting the execution of
the page programming command. The application must ensure that the required number
of data bytes is written into the TX Buffer fast enough as long as the command is
executed without a TX Buffer overflow or underrun.
The QuadSPI module sets the QSPI_FR[TBFF] flag so long as the TX Buffer is not full
and can accept more data.
When the QuadSPI module tries to pull data out of an empty TX Buffer the TX Buffer
underrun is signaled by the QSPI_FR[TBUF] flag.The TX buffer underrun flag is also
asserted when TX buffer contains less than 128 bits of data and QuadSPI module tries to
pull out data from it. The current IP Command leading to the underrun condition is
continued until the specified number of bytes has been sent to the serial flash device, in
the underrun condition when QuadSPI module tries to pull out data of empty TX buffer,
the data transferred is all F's i.e. once the underrun flag is set under this condition, it will
return F's until the required number of bytes are not sent. This has been done to ensure
that the software need not to erase whole sector after underrun, just reprogramming from
Functional Description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
902
NXP Semiconductors
Содержание MWCT101 S Series
Страница 2: ...MWCT101xS Series Reference Manual Rev 3 07 2019 2 NXP Semiconductors...
Страница 42: ...MWCT101xS Series Reference Manual Rev 3 07 2019 42 NXP Semiconductors...
Страница 50: ...Conventions MWCT101xS Series Reference Manual Rev 3 07 2019 50 NXP Semiconductors...
Страница 70: ...Aliased bit band regions MWCT101xS Series Reference Manual Rev 3 07 2019 70 NXP Semiconductors...
Страница 78: ...Pinout diagrams MWCT101xS Series Reference Manual Rev 3 07 2019 78 NXP Semiconductors...
Страница 96: ...WCT101xS safety concept MWCT101xS Series Reference Manual Rev 3 07 2019 96 NXP Semiconductors...
Страница 130: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 130 NXP Semiconductors...
Страница 200: ...Initialization application information MWCT101xS Series Reference Manual Rev 3 07 2019 200 NXP Semiconductors...
Страница 284: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 284 NXP Semiconductors...
Страница 430: ...Functional Description MWCT101xS Series Reference Manual Rev 3 07 2019 430 NXP Semiconductors...
Страница 472: ...Application Information MWCT101xS Series Reference Manual Rev 3 07 2019 472 NXP Semiconductors...
Страница 508: ...Reset memory map and register descriptions MWCT101xS Series Reference Manual Rev 3 07 2019 508 NXP Semiconductors...
Страница 528: ...Module clocks MWCT101xS Series Reference Manual Rev 3 07 2019 528 NXP Semiconductors...
Страница 634: ...SRAM configuration MWCT101xS Series Reference Manual Rev 3 07 2019 634 NXP Semiconductors...
Страница 696: ...Initialization and application information MWCT101xS Series Reference Manual Rev 3 07 2019 696 NXP Semiconductors...
Страница 818: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 818 NXP Semiconductors...
Страница 960: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 960 NXP Semiconductors...
Страница 970: ...Memory Map and Register Definition MWCT101xS Series Reference Manual Rev 3 07 2019 970 NXP Semiconductors...
Страница 992: ...ADC calibration scheme MWCT101xS Series Reference Manual Rev 3 07 2019 992 NXP Semiconductors...
Страница 1118: ...Application information MWCT101xS Series Reference Manual Rev 3 07 2019 1118 NXP Semiconductors...
Страница 1294: ...Initialization Procedure MWCT101xS Series Reference Manual Rev 3 07 2019 1294 NXP Semiconductors...
Страница 1348: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 1348 NXP Semiconductors...
Страница 1366: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 1366 NXP Semiconductors...
Страница 1514: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 1514 NXP Semiconductors...
Страница 1726: ...Debug and security MWCT101xS Series Reference Manual Rev 3 07 2019 1726 NXP Semiconductors...
Страница 1740: ...Initialization application information MWCT101xS Series Reference Manual Rev 3 07 2019 1740 NXP Semiconductors...
Страница 1760: ...MWCT101xS Series Reference Manual Rev 3 07 2019 1760 NXP Semiconductors...