NXP Semiconductors MWCT101 S Series, Справочное руководство

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Field Function
M_CEN Enables the peripheral clock to the module timers.
• The Module Clock Enable bit must be asserted when accessing these registers:
• Module Status Register (MSR)
• Set Timer Enable Register (SETTEN)
• Clear Timer Enable Register (CLRTEN)
• Timer Value Registers (TVAL
n )
• Current Timer Value Registers (CVAL n )
• Timer Control Registers (TCTRL n )
• Both the bus clock and peripheral clock must be enabled to allow for clock synchronization and
updating the above registers.
• Acessing the above mentioned registers while the Module Clock Enable bit (M_CEN) = '0', will
assert a transfer error for that bus cycle.
• Writing to Current Timer Value (CVAL n ) registers and Reserved registers will always generate a
transfer error.
NOTE: There may be additional clock gating bits in your device that gate the peripheral clock to the
LPIT module. Ensure that those additional clock gating bits are configured appropriately, to
enable the peripheral clock to the LPIT module.
0b - Disable peripheral clock to timers
1b - Enable peripheral clock to timers
42.4.1.5 Module Status Register (MSR)
42.4.1.5.1 Offset
Register Offset
MSR Ch
42.4.1.5.2 Function
NOTE
Unless the Module Clock Enable bit (MCR[M_CEN]) is set
(=1, peripheral clock to timers is enabled), reading or writing
the Module Status register will generate a transfer error.
Chapter 42 Low Power Interrupt Timer (LPIT)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1305