NXP Semiconductors MWCT101 S Series, Справочное руководство

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• Can be selected as the clock source for the MCU system clocks
• 2 programmable post-dividers clock outputs, which can be used as clock sources
for other on-chip peripherals
• 2 Internal reference clock (IRC) generators:
• Fast IRC clock with programmable High and Low frequency range
• Either the slow or the fast clock can be selected as the clock source for the MCU
system clocks
• 2 programmable post-divider clock outputs for each IRC, which can be used as
clock sources for other on-chip peripherals
• System Crystal Oscillator:
• Used as the source for the System PLL
• Can be selected as the clock source for the MCU system clocks
• Clock monitor with reset and interrupt request capability for SPLL, SOSC, clocks
• Lock detector with interrupt request capability for use with the SPLL
• Each of the clock sources have reference dividers for clocking on-chip modules and
peripherals, namely:
• SPLLDIV1_CLK / SPLLDIV2_CLK
• FIRCDIV1_CLK / SCG_FIRCDIV2_CLK
• SIRCDIV1_CLK / SIRCDIV2_CLK
• SOSCDIV1_CLK / SOSCDIV2_CLK
See the Clock Distribution Chapter for more information.
26.3 Memory Map/Register Definition
This section includes the memory map and register definition.
The SCG registers can only be written when in supervisor mode. Write accesses when in
user mode will result in a bus transfer error. Read accesses may be performed in both
supervisor and user mode.
NOTE
For any writeable SCG registers, only 32-bit writes are allowed.
8-bit or 16-bit writes will result in transfer errors.
Memory Map/Register Definition
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
532 NXP Semiconductors