MPC555
/
MPC556
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
MOTOROLA
USER’S MANUAL
Rev. 15 October 2000
15-8
If a supervisor privilege address space is accessed in user mode, the module returns
a bus error.
All MIOS1 unimplemented locations within the addressable range, return a logic 0
when accessed. In addition, the internal TEA (transfer error acknowledge) signal is as-
serted.
All unused bits within MIOS1 registers return a 0 when accessed.
15.7 MIOS1 I/O Ports
Each pin of each submodule can be used as an input, output, or I/O port:
15.8 MIOS Bus Interface Submodule (MBISM)
The MIOS bus interface submodule (MBISM) is used as an interface between the
MIOB (modular I/O bus) and the IMB3. It allows the CPU to communicate with the
MIOS1 submodules.
15.8.1 MIOS Bus Interface (MBISM) Registers
is the address map for the MBISM submodule.
15.8.1.1 MIOS1 Test and Pin Control Register
Table 15-1 MIOS1 I/O Ports
Submodule
Number
Type
MPIOSM
16
I/O
MMCSM
2
I
MDASM
1
I/O
MPWMSM
1
I/O
Table 15-2 MBISM Address Map
Address
Register
0x30 6800
MIOS1 Test and Pin Control Register (MIOS1TPCR)
See
for bit descriptions.
0x30 6802
Reserved (MIOS1 Vector Register in some implementations)
0x30 6804
MIOS1 Module Version Number Register (MIOS1VNR)
See
for bit descriptions.
0x30 6806
MIOS1 Module Control Register (MIOS1MCR)
See
for bit descriptions.
0x30 6808 –
0x30 680E
Reserved
MIOS1TPCR
— Test and Pin Control Register
0x30 6800
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LSB
15
TEST
RESERVED
VF
VFLS
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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Freescale Semiconductor, Inc.
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