NEC PG-FPL3, Руководство пользователя

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User’s Manual U17454EJ1V0UM
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CHAPTER 7 NOTES ON TARGET SYSTEMS
This chapter explains the basic notes on the target system for rewriting the flash memory in the microcontroller
using the FPL3.
CPU Pin Design Proposal
Do not connect the RESET signal generator on the target system to the RESET signal of the FPL3. Otherwise,
a signal conflict will occur. To avoid the conflict, isolate the RESET signal generator from the RESET signal of
the FPL3.
Do not generate RESET while the FPL3 is connected. This must be especially noted in a system that uses an
external watchdog timer.
RESET
Connect the RESET signal of the FPL3 at a point where the status of the programmer RESET signal and that of
the CPU RESET pin are the same.
Correct connection:
CPU
FPL3 RESET
RESET
Avoid the following RESET signal connection.
•
Connection to a point where the target CPU RESET rise time is slower than the FPL3 RESET rise time.
Incorrect connection:
CPU
OC
FPL3 RESET
RESET
It takes time for the CPU RESET pin to go high after the FPL3 RESET level goes from low to high.