CHAPTER 5 CLOCK GENERATOR
Preliminary User’s Manual U19014EJ1V0UD
109
Table 5-4. CPU Clock Transition and SFR Register Setting Examples (2/3)
(3) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
AMPH
Note
EXCLK OSCSEL MSTOP OSTC
Register
XSEL
Note
MCM0
(B)
→
(C) (X1 clock: f
XH
≤
10 MHz)
0
0
1
0
Must be
checked
1 1
(B)
→
(C) (external main clock: f
XH
≤
10 MHz)
0
1
1
0
Must not be
checked
1 1
(B)
→
(C) (X1 clock: 10 MHz < f
XH
)
1 0 1 0
Must be
checked
1 1
(B)
→
(C) (external main clock: 10 MHz < f
XH
) 1 1 1 0
Must not be
checked
1 1
Unnecessary if these registers
are already set
Unnecessary if the
CPU is operating
with the high-speed
system clock
Note
The value of this flag can be changed only once after a reset release. This setting is not necessary if it has
already been set.
Cautions 1.
Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET)).
2. CPU clock cannot changes from high-speed system clock (C) to internal high-speed oscillation
clock (B)
Remarks 1.
(A) to (E) in Table 5-4 correspond to (A) to (E) in Figure 5-14.
2.
EXCLK, OSCSEL, AMPH:
Bits 7, 6 and 0 of the clock operation mode select register (OSCCTL)
MSTOP:
Bit 7 of the main OSC control register (MOC)
XSEL, MCM0:
Bits 2 and 0 of the main clock mode register (MCM)
RSTS, RSTOP: Bits 7 and 0 of the internal oscillation mode register (RCM)
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