CHAPTER 5 CLOCK GENERATOR
Preliminary User’s Manual U19014EJ1V0UD
108
Table 5-4 shows transition of the CPU clock and examples of setting the SFR registers.
Table 5-4. CPU Clock Transition and SFR Register Setting Examples (1/3)
(1) CPU operating with internal high-speed oscillation clock (B) after reset release (A)
Status Transition
SFR Register Setting
(A)
→
(B)
SFR registers do not have to be set (default status after reset release).
(2) CPU operating with high-speed system clock (C) after reset release (A)
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
AMPH EXCLK OSCSEL
MSTOP OSTC
Register
XSEL MCM0
(A)
→
(B)
→
(C) (X1 clock: f
XH
≤
10
MHz)
0 0 1 0
Must be
checked
1 1
(A)
→
(B)
→
(C)
(external main clock: f
XH
≤
10 MHz)
0 1 1 0
Must not be
checked
1 1
(A)
→
(B)
→
(C) (X1 clock: 10 MHz < f
XH
)
1 0 1 0
Must be
checked
1 1
(A)
→
(B)
→
(C)
(external main clock: 10 MHz < f
XH
)
1 1 1 0
Must not be
checked
1 1
Caution
Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET)).
Remarks 1.
(A) to (E) in Table 5-4 correspond to (A) to (E) in Figure 5-14.
2.
EXCLK, OSCSEL, AMPH:
Bits 7, 6 and 0 of the clock operation mode select register (OSCCTL)
MSTOP:
Bit 7 of the main OSC control register (MOC)
XSEL, MCM0:
Bits 2 and 0 of the main clock mode register (MCM)
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