Preliminary User’s Manual U19014EJ1V0UD
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CHAPTER 24 CAUTIONS FOR WAIT
24.1 Cautions for Wait
This product has two internal system buses.
One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware.
Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data
may be passed if an access to the CPU conflicts with an access to the peripheral hardware.
When accessing the peripheral hardware that may cause a conflict, therefore, the CPU repeatedly executes
processing, until the correct data is passed.
As a result, the CPU does not start the next instruction processing but waits. If this happens, the number of
execution clocks of an instruction increases by the number of wait clocks (for the number of wait clocks, see
Table 24-
12
). This must be noted when real-time processing is performed.
24.2 Peripheral Hardware That Generates Wait
Table 24-1 lists the registers that issue a wait request when accessed by the CPU, and the number of CPU wait
clocks.
Table 24-1. Registers That Generate Wait and Number of CPU Wait Clocks
Peripheral
Hardware
Register
Access
Number of Wait Clocks
Serial interface
UART6
ASIS6
Read
1 clock (fixed)
Remark
The clock is the CPU clock (f
CPU
).
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