CHAPTER 17 LOW-VOLTAGE DETECTOR
Preliminary User’s Manual U19014EJ1V0UD
438
(2) Low-voltage
detection
level selection register (LVIS)
This register selects the low-voltage detection level.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation input sets LVIS to 00H.
Figure 17-3. Format of Low-Voltage Detection Level Selection Register (LVIS)
0
LVIS0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
Symbol
LVIS
Address: FFBFH After reset: 00H R/W
LVIS0 Detection
level
0 V
LVI0
(4.24 V
±
0.1 V)
1 V
LVI1
(4.09 V
±
0.1 V)
Cautions 1. Be sure to clear bits 1 to 7 to 0.
2. Do not change the value of LVIS during LVI operation.
(3) Port mode register 12 (PM12)
When using the P120/INTP0 pin for external low-voltage detection potential input, set PM120 to 1. At this time,
the output latch of P120 may be 0 or 1.
PM12 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PM12 to FFH.
Figure 17-4. Format of Port Mode Register 12 (PM12)
0
PM120
1
PM121
2
PM122
3
1
4
1
5
1
6
1
7
1
Symbol
PM12
Address: FF2CH After reset: FFH R/W
PM12n
P12n pin I/O mode selection (n = 0 to 2)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
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