NEC mPD78F0730, Предварительное руководство пользователя

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CHAPTER 3 CPU ARCHITECTURE
Preliminary User’s Manual U19014EJ1V0UD
31
Figure 3-1. Memory Map
Special function registers
(SFR)
256
×
8 bits
Internal high-speed RAM
1024
×
8 bits
Internal expansion RAM
2048
×
8 bits
USB area
303
×
8 bits
General-purpose
registers
32
×
8 bits
Reserved
Reserved
Flash memory
16384
×
8 bits
Boot cluster 0
Note 2
Boot cluster 1
Program
memory space
Data memory
space
Program RAM area
RAM space in
which instruction
can be fetched
Vector table area
64
×
8 bits
CALLT table area
64
×
8 bits
Program area
1905
×
8 bits
Option byte area
Note 1
5
×
8 bits
CALLF entry area
2048
×
8 bits
Program area
Program area
Option byte area
Note 1
5
×
8 bits
On-chip debug security
ID setting area
Note 1
10
×
8 bits
On-chip debug security
ID setting area
Note 1
10
×
8 bits
F F F F H
F F 0 0 H
F E F F H
F E E 0 H
F E D F H
F B 0 0 H
F A F F H
F 8 0 0 H
F 7 F F H
F 9 D 1 H
F 9 D 0 H
F 0 0 0 H
E F F F H
4 0 0 0 H
3 F F F H
0 0 0 0 H
0 8 0 0 H
0 7 F F H
1 0 0 0 H
0 F F F H
0 0 4 0 H
0 0 3 F H
0 0 0 0 H
0 0 8 5 H
0 0 8 4 H
3 F F F H
0 0 8 0 H
0 0 7 F H
1 0 8 5 H
1 0 8 4 H
1 0 8 0 H
1 0 7 F H
0 0 8 F H
0 0 8 E H
1 0 8 F H
1 0 8 E H
1 F F F H
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H, and the on-chip debug security
IDs to 0085H to 008EH.
When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H, and the
on-chip debug security IDs to 0085H to 008EH and 1085H to 108EH.
2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 19.8 Security
Setting ).
Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers,
see Table 3-2 Correspondence Between Address Values and Block Numbers in Flash Memory .
Block 00H
Block 01H
Block 0FH
1 KB
3 F F F H
0 7 F F H
0 0 0 0 H
0 4 0 0 H
0 3 F F H
3 C 0 0 H
3 B F F H
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