NEC mPD78F0730, Предварительное руководство пользователя

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Preliminary User’s Manual U19014EJ1V0UD
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3.4 Operand Address Addressing ................................................................................................ 51
3.4.1 Implied addressing .....................................................................................................................51
3.4.2 Register addressing ...................................................................................................................52
3.4.3 Direct addressing .......................................................................................................................53
3.4.4 Short direct addressing ..............................................................................................................54
3.4.5 Special function register (SFR) addressing................................................................................55
3.4.6 Register indirect addressing.......................................................................................................56
3.4.7 Based addressing ......................................................................................................................57
3.4.8 Based indexed addressing.........................................................................................................58
3.4.9 Stack addressing .......................................................................................................................59
CHAPTER 4 PORT FUNCTIONS ........................................................................................................... 60
4.1 Port Functions.......................................................................................................................... 60
4.2 Port Configuration ................................................................................................................... 61
4.2.1 Port 0 .........................................................................................................................................62
4.2.2 Port 1 .........................................................................................................................................64
4.2.3 Port 3 .........................................................................................................................................70
4.2.4 Port 6 .........................................................................................................................................72
4.2.5 Port 12 .......................................................................................................................................73
4.3 Registers Controlling Port Function...................................................................................... 76
4.4 Port Function Operations........................................................................................................ 79
4.4.1 Writing to I/O port .......................................................................................................................79
4.4.2 Reading from I/O port.................................................................................................................79
4.4.3 Operations on I/O port................................................................................................................79
4.5 Settings of Port Mode Register and Output Latch When Using Alternate Function ........ 80
CHAPTER 5 CLOCK GENERATOR ...................................................................................................... 81
5.1 Functions of Clock Generator ................................................................................................ 81
5.2 Configuration of Clock Generator.......................................................................................... 82
5.3 Registers Controlling Clock Generator ................................................................................. 84
5.4 System Clock Oscillator.......................................................................................................... 94
5.4.1 X1 oscillator ...............................................................................................................................94
5.4.2 Internal high-speed oscillator .....................................................................................................96
5.4.3 Internal low-speed oscillator.......................................................................................................96
5.4.4 Prescaler....................................................................................................................................96
5.5 Clock Generator Operation ..................................................................................................... 97
5.6 Controlling Clock ..................................................................................................................... 99
5.6.1 Controlling high-speed system clock..........................................................................................99
5.6.2 Example of controlling internal high-speed oscillation clock.....................................................102
5.6.3 Example of controlling internal low-speed oscillation clock ......................................................104
5.6.4 Example of controlling USB clock ............................................................................................105
5.6.5 Clocks supplied to CPU and peripheral hardware....................................................................106
5.6.6 CPU clock status transition diagram ........................................................................................107
5.6.7 Condition before changing CPU clock and processing after changing CPU clock ...................110
5.6.8 Time required for switchover of CPU clock and main system clock .........................................111
5.6.9 Conditions before clock oscillation is stopped..........................................................................112
5.6.10 Peripheral hardware and source clocks ...................................................................................112
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