Programming Model
MOTOROLA
Synchronous Serial Interface (SSI)
30-19
30.3.7.1 I
2
S Mode Selection
The SCSR contains two bits, the I
2
S Mode Select (I2S MODE1 and I2S MODE0) bits, that determine the
mode of the SSI module. This section explains how the mode of the module affects the bits in the other SSI
registers. Table 30-8 summarizes the mode settings.
In normal mode operation, no register bits are forced to any particular state internally and the SSI can be
programmed to work in any operating condition.
When entering I
2
S modes (I
2
S master or I
2
S slave), several control bits are fixed in the hardware. Attempts
to write to these bits when in I
2
S master or I
2
S slave mode are ignored. These bits are described in
Table 30-9.
The user must configure the bit clock in the STCCR and the SRCCR.
TFE
Bit 0
Transmit FIFO Empty
—Indicates that the data level in the
transmit FIFO reaches the Transmit FIFO Empty Water Mark.
The Water Mark is defined in the TFWM field of the SSI FIFO
Control/Status Register (SFCSR). The transmit FIFO must be
enabled or TFE is meaningless.
When TFE is set, data can be written to the transmit FIFO via the
STX register.
Note:
An interrupt is generated only when both the TFE and
TIE (of the STCR) are set and the transmit FIFO is enabled (the
TFEN bit in the STCR is set).
0 = Data level in the transmit
FIFO exceeds Water
Mark
1 = Data level in the transmit
FIFO below Watermark
Table 30-8. I
2
S Mode Selection
I2S_MODE [1]
I2S_MODE [0]
Remark
0
0
Normal mode
0
1
I
2
S master mode
1
0
I
2
S slave mode
1
1
Normal mode
Table 30-9. I
2
S Master or I
2
S Slave Mode Settings
I
2
S Mode
Bit
Name
Register
Location
Forced
Value
Function
Master or save
SYN
SCSR [12]
1
Synchronous mode enabled
Master or save
NET
SCSR [11]
1
Network mode enabled
Master or save
TSHFD
STCR [4]
0
Transmission direction is MSB first
Master or save
RSHFD
SRCR [4]
0
Receive direction is MSB first
Master or save
TSCKP
STCR [3]
1
Falling edge of bit clock clocks data out
Table 30-7. SSI Control/Status Register Description (Continued)
Name
Description
Settings
Содержание DragonBall MC9328MX1
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