Motorola DragonBall MC9328MX1, Справочное руководство

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24-62 MC9328MX1 Reference Manual MOTOROLA
SDRAM Memory Controller
The values programmed into the SDRAM Mode register for example 1 are as follows:
• Sequential burst (BT = 0)
• Burst length of 8 (BL = 011), not optional
• Single word writes (WB = 1), not optional
• 2 Clock latency (LTMODE = 010)
When the Mode register value has been determined, it must be converted to an address. The Mode register
is written via the address bus and the memory data sheet specifies the SDRAM address bits on which to
place the data. One final transformation is necessary to align the address to the multiplexed outputs of the
SDRAM controller. Memory density and bus width determine the alignment of the SDRAM to the
controller pins and must be considered during the calculation.
The first step is to determine the value of the 256 Mbit SDRAM Mode register and convert this into an
SDRAM address. Table 24-42 is the same as Table 24-40, however it includes the values for this 256 Mbit
SDRAM example. This table illustrates what value needs to be placed on the address bus to the SDRAM
memory.
The next step is to determine that the proper value is written to the MC9328MX1 internal address bus to
ensure that the SDRAM controller’s ROW/COLUMN ADDRESS MUX writes these values to the correct
address pins of the MC9328MX1’s external address bus and then to the SDRAM memory. Table 24-39
simplifies this procedure by allowing the user to simply plug in the Mode register bits into this table
therefore generating the correct address to write from the MC9328MX1. Referring to Table 24-39 and
locating the proper SDRAM memory density (in this case the 16M
×
16 SDRAM), proceed by plugging in
the Mode register bits into this table. Table 24-43 illustrates this procedure.
Table 24-43 assumes CSD0 is being used as the chip-select for the SDRAM memory, therefore the
chip-select base address bits, A'31 through A'24, are set to 00001000 for the memory map region
0x08000000. As a result, for this example, the final value (in hexadecimal format) written to the
MC9328MX1 internal address for proper translation to the SDRAM memory mode register is
0x08111800. The procedure would then be to issue a Set Mode Register Command to the SDRAM
memory, followed by an access (either READ or WRITE) to the SDRAM memory at address 0x08111800.
Table 24-42. 256 Mbit SDRAM Mode Register with Values
SDRAM Address
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Mode Register Bit M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0
Content Reserved WB Reserved CAS latency BT Burst length
Value 0 0 0 1 0 0 0 1 0 0 0 1 1
Table 24-43. MC9328MX1 Address Calculation for Given Mode Register Values
Internal
Address
A'
31
A'
30
A'
29
A'
28
A'
27
A'
26
A'
25
A'
24
A'
23
A'
22
A'
21
A'
20
A'
19
A'
18
A'
17
A'
16
A'
15
A'
14
A'
13
A'
12
A'
11
A'
10
A'
9
A'
8
A'
7
A'
6
A'
5
A'
4
A'
3
A'
2
A'
1
A'
0
Mode
Register
Bit
0 0 0 0 X X 0 0
M1
3
M1
2
M1
1
M1
0
M9 M8 M7 M6 M5 M4 M3 M2 M1 M0
0 0 0 0 0 0 0 0 0 0
Mode
Register
Bit
Value
0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0