Motorola DragonBall MC9328MX1, Справочное руководство

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12-12 MC9328MX1 Reference Manual MOTOROLA
Phase-Locked Loop and Clock Controller
12.5.4.1 System PLL Control Register 0
The System PLL Control Register 0 (SPCTL0) is a 32-bit register that controls the operation of the System
PLL. The SPCTL0 control bits are described in the following sections. A delay of 30 System PLLCLK
cycles is required between two write accesses to SPCTL0 register. The following is a procedure for
changing the System PLL settings:
1. Program the desired values of PD, MFD, MFI, and MFN into the SPCTL0.
2. Set the SPLL_RESTART bit in the CSCR (it will self-clear).
3. New PLL settings will take place.
SPCTL0 System PLL Control Register 0
Addr
0x0021B00C
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PD MFD
TYPE r r rw rw rw rw rw rw rw rw rw rw rw rw rw rw
RESET
0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1
0x043F
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MFI MFN
TYPE r r rw rw rw rw rw rw rw rw rw rw rw rw rw rw
RESET
0 0 0 1 0 1 0 0 0 0 1 1 0 1 1 1
0x1437
Table 12-12. System PLL Control Register 0 Description
Name Description Settings
Reserved
Bits 31–30 Reserved—These bits are reserved and should read 0.
PD
Bits 29–26
Predivider Factor —Defines the predivider factor (PD) that is applied to the
PLL input frequency. PD is an integer between 0 and 15 (inclusive). The
System PLL oscillates at a frequency determined by Equation 12-1. The PD is
chosen to ensure that the resulting VCO output frequency remains within the
specified range. When a new value is written into the PD bits, the PLL loses its
lock: after a time delay, the PLL re-locks.
0000 = 0
0001 = 1
…
1111 = 15
MFD
Bits 25–16
Multiplication Factor (Denominator Part) —Defines the denominator part of
the BRM value for the MF. When a new value is written into the MFD9–MFD0
bits, the PLL loses its lock: after a time delay, the PLL re-locks.
0x000 = Reserved
0x001 = 1
…
0x3FF = 1023
Reserved
Bits 15–14 Reserved—These bits are reserved and should read 0.