675
S.TO, SP.TO
9
2
3
4
4
6
7
8
9.1
W
riting to
the CPU Shar
ed Memor
y of H
ost C
P
U
9.1.1
S
.TO, SP.TO
Writing data to CPU shared memory can be performed using the intelligent function module device.
For intelligent function module device, refer to the QnUCPU User's Manual (Function Explanation, Program Fundamentals)
or Qn(H)/QnPH/QnPRHCPU User's Manual (Function Explanation, Program Fundamentals).
Operat
i
on
E
rror
In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Program
E
xamp
l
e
(1) The following program stores 10 points of data from D0 into address 800
H
of the CPU shared memory of CPU No. 1
when X0 is turned ON.
[Ladder Mode]
[List Mode]
Error
code
Error details
Q00J/
Q00/
Q01
QnH
QnPH QnPRH
QnU
LCPU
2107
When the head I/O number (n1) of the host CPU is other than that of
the host CPU.
––
––
––
––
2110
No CPU module is installed at the position specified for the head I/O
number of the CPU module.
––
––
4002
When the specified instruction is improper.
––
––
4003
When the number of devices specified is incorrect.
––
––
4004
When an Unavailable device is specified.
––
––
4100
When the head I/O number (n1) of the host CPU is other than 3E0
H
/
3E1
H
/3E2
H
/3E3
H
.
––
––
4101
When the host CPU operation information area, system area, or host
CPU refresh area is specified to the CPU shared memory address (n2)
of the write destination.
––
––
––
––
When the number of write points (n4) is outside the specified range of
the setting data.
When the head of the CPU shared memory address (n2) of the write
destination host CPU exceeds the CPU shared memory address range.
When the CPU shared memory address (n2) + the number of write
points (n4) of the write destination host CPU exceeds the CPU shared
memory address range.
When the head number of the devices (n3) where the data to be written
is the number of write points (n4) exceeds the device range.
––
––
4111
When the host CPU operation information area, system area, or host
CPU refresh area is specified to the CPU shared memory address (n2)
of the write destination.
––
––
––
––
4112
When the head I/O number (n1) of the host CPU is other than that of
the host CPU.
––
––
––
––
I
nstruct
i
on
De
vi
ce
Step