692
(8) Program example when the multiple CPU high-speed transmission dedicated instructions are executed to CPU modules
by turns
When the multiple CPU high-speed transmission dedicated instructions are executed to Universal model QCPUs by
turns, release an interlock to prevent the concurrent execution.
Use the cyclic transmission area device (from U3En\G10000) as an interlock.
The following shows a program example when the multiple CPU high-speed transmission dedicated instructions are
executed at CPU No.s 1 and 2 by turns.
Program example when the multiple CPU high-speed transmission dedicated instruction is executed at CPU No.1
SM
4
02
T
urn
-
on
for
one
scan
after
R
UN
MOV
K
7
SD797
Max
i
mum
number
of
used
b
l
ocks
(CP
U N
o
.
2)
X0
S
ET
M0
Dur
i
ng
execut
i
on
of
the
DDWR
i
nstruct
i
on
Wr
i
te
command
U
3
E
0
\
G10000
.
0
i
s
turned
on
w
h
il
e
CP
U N
o
.
1
i
s
execut
i
ng
the
DP
.
DDWR
i
nstruct
i
on
.
M0
U
3
E
1
\
G10000
.
0
SM797
Dur
i
ng
execut
i
on
of
the
DDWR
i
nstruct
i
on
CP
U N
o
.
2
i
s
dur
i
ng
execut
i
on
of
the
i
nstruct
i
on
N
umber
of
used
b
l
ocks
i
nformat
i
on
(CP
U N
o
.
2)
S
ET
G10000
.
0
U
3
E
0
\
CP
U N
o
.
1
i
s
dur
i
ng
execut
i
on
of
the
i
nstruct
i
on
MOV
K
100
D1
N
umber
of
w
r
i
te
po
i
nts
DP
.
DDWR
H
3
E
1
D0
ZR100
ZR100
M1
Comp
l
et
i
on
status
Comp
l
et
i
on
de
vi
ce
RS
T
M0
Dur
i
ng
execut
i
on
of
the
DDWR
i
nstruct
i
on
U
3
E
0
\
G10000
.
0
i
s
turned
on
w
h
il
e
CP
U N
o
.
1
i
s
execut
i
ng
the
DP
.
DDWR
i
nstruct
i
on
.
S
ET
G10000
.
0
U
3
E
0
\
CP
U N
o
.
1
i
s
dur
i
ng
of
the
i
nstruct
i
on
M1
Comp
l
et
i
on
de
vi
ce