674
S.TO, SP.TO
F
unct
i
on
(1) Writes device data of words n3 to n4 to the CPU shared memory address specified by n2 of the host CPU module or later
address.
When writing is completed, the completion bit specified by turns ON.
(a) CPU shared memory address of the Basic model QCPU
(b) CPU shared memory address of the High Performance model QCPU, Process CPU and Universal model QCPU
*2
*1:
Usable as a user free area when auto refresh setting is not made.
In addition, even when auto refresh setting is made, the auto refresh send range or later is usable as a user free area.
*2:
Data cannot be written to the multiple CPU high speed transmission area of the Universal model QCPU with the S(P).TO
instruction.
(2) When the number of write points is 0, no processing is performed and the completion device does not turn ON, either.
(3) The S.TO instruction can be executed once to one scan for each CPU.
When execution condition is established at two or more places at the same time, the S.TO instruction executed later is
not processed since handshake is established automatically.
(4) The number of data that can be written varies depending on the target CPU module.
CPU module
Number of Write Points
Basic model QCPU
1 to 320
High Performance model QCPU
Process CPU
1 to 256
Universal model QCPU
1 to 2048
D
De
v
ice memory
Writes the
data of n4
w
ords
Host CP
U
n4
n3
CP
U
shared memory
of host CP
U
(n1)
n2
H
ost
CP
U
operat
i
on
i
nformat
i
on
area
CP
U
shared
memory
address
System
area
H
ost
CP
U
refresh
area
*1
U
ser
free
area
0(0
H
)
96(60
H
)
192(C0
H
)
511(1
FF
H
)
Wr
i
te
des
i
gnat
i
on
proh
i
b
i
ted
area
Wr
i
te
des
i
gnat
i
on
perm
i
tted
area
CP
U
shared memory address
0(0
H
)
512(200
H
)
2048(800
H
)
4095(0FFF
H
)
Host CP
U
operation information area
System area
Host CP
U
refresh area
*1
U
ser free area
Write designation
prohibited area
Write designation
permitted area