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Workstation 4 and 4 LX Field Service Guide 4-5
WS4 LX Technical Overview
LX800 Processor and TFT Controller
• The 64-bit DDR SDRAM Interface as implemented on the LX System Board,
supports unbuffered DDR 333/400 DIMMs up to up to 1GB.
• Unified Memory Architecture (UMA), UMA enables up to 2GBps memory
bandwidth while using single memory interface. The DDR Memory array
contains both the main system memory and the graphics frame buffer.
GeodeLink Control Processor
The GeodeLink Control Processor is used for software debugging and performance
analysis.
GeodeLink PCI Bridge
The GeodeLink PCI Bridge (GLPCI) module provides the PCI interface for the
LX800 system. It is comprised of five major sections or blocks, briefly described
below.
GeodeLink Interface Block
The GeodeLink Interface Block provides a conversion layer between the
GeodeLink Interface Unit 1 (GLIU1) and the Transaction Forwarding Block.
FIFO/Synchronous Block
The FIFO module consists of a group of in-bound and out-bound FIFOs. Each
FIFO provides a simple, synchronous interfaces to read and write requests.
Transaction Forwarding
The Transaction Forwarding block receives, processes and forwards transaction
requests and responses between the GeodeLink Interface and PCI Bus Blocks.
Transaction ordering rules are implemented and write gathering and read
pre-fetching are performed as required.
PCI Bus Interface Block
The PCI Bus Interface provides a protocol conversion layer between the
transaction forwarding block and the PCI bus. The master and target portions of
this block operate independently.
The PCI Bus Interface Block implements the logic to generate PCI configuration
cycles. The standard mechanism for generating PCI Configuration cycles (as
described in the PCI 2.2 Specification) is used.
PCI Bus Arbiter
The PCI Arbiter implements a fair arbitration scheme with special support for the
CD5536 companion device. By default it operates as a simple round robin arbiter
that rotates three request/grant priorities in a circular fashion.