USER MANUAL
Document reference MAODS301/E
SpeedSys300 ODS301 overspeed detection system
Edition 4 - May 2022
F - 18
Parameters and configuration settings
APPENDIX F: SPEEDSYS300 ODS301 MODBUS REGISTER DEFINITIONS
4512
e_latch_mask_adm
uint32
Level 1
Error latching mask. Bit set means
SpeedSys300 ODS301 stays in safe state
even if error reason vanishes:
B0 – User level 0 parameter CRC
B1 – User level 1 parameter CRC
B2 – User level 2 parameter CRC
B3 – n.u.
B4 – n.u.
B5 – n.u.
B6 – n.u.
B7 – Sensor error (short/break)
B8 – n.u.
B9 – Bad pulses
B10 – Slave communication failed
B11 – Threshold readback error
B12 – Slave supplies
B13 – Aout readback error
B14 – Rail supply out of range
B15 – 24 V supply out of range
B16 – Master Vcc out of range
B17 – Relay PST error
B18 – Parameter value invalid
B19 – Master temperature over/under range
B20 – USB interface active
B21 – n.u. (initial safe always latching)
B22 – UART watchdog
B23 – Slave runtime watchdog error
B24 – Slave startup watchdog error
B25-B31 – n.u.
This mask is OR-ed with corresponding
mask in factory diagnostic parameter set.
4514
proof_chk
uint16
0 to 1
Level 1
Proof check active:
0 – Not active (only error reset)
1 – Active (proof check and error reset).
4515
USB_active
uint16
0 to 1
Level 1
USB activate action:
0 – No action
1 – Enter safe state (error bit B20).
4516
sif_disable
uint16
Level 1
B0 – Disable analog output check
B1 – Disable analog output error signalling
(no err_our in safe state)
B2 – Disable initial safe state after power
cycle or watchdog reset.
4517
crc_diag_adm
uint16
Level 1
Parameter block CRC
Table F-11:
SpeedSys300 ODS301 Modbus registers – diagnostics configuration – admin (continued)
Address
Name
Data
type
Range
Access
Description
Содержание vibro-meter SpeedSys300 ODS301
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