Keithley 6517A, Руководство пользователя

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Figure 2-39 V-source (FVMI configuration) ............................................................................................................... 2-48
Figure 2-40 Typical 2V analog output connections ..................................................................................................... 2-51
Figure 2-41 Typical preamp out connections ............................................................................................................... 2-53
Figure 2-42 Electrometer input circuitry (external feedback mode) ............................................................................ 2-54
Figure 2-43 Shielded fixture construction .................................................................................................................... 2-55
Figure 2-44 “Transdiode” logarithmic current configuration ...................................................................................... 2-57
Figure 2-45 Non-decade current gains ......................................................................................................................... 2-58
Figure 2-46 Equivalent input impedance with zero check enabled ............................................................................. 2-59
Figure 2-47 Connections; diode leakage current test ................................................................................................... 2-61
Figure 2-48 Default measurement points; diode leakage current test .......................................................................... 2-61
Figure 2-49 Connections; capacitor leakage current test ............................................................................................. 2-62
Figure 2-50 Connections; cable insulation resistance test ........................................................................................... 2-63
Figure 2-51 Test circuit; resistor voltage coefficient test ............................................................................................. 2-64
Figure 2-52 Alternating polarity resistance/resistivity test .......................................................................................... 2-65
Figure 2-53 Connections; surface insulation resistance test ........................................................................................ 2-66
Figure 2-54 Default measurement points; square wave sweep test ............................................................................. 2-67
Figure 2-55 Default measurement points; staircase sweep test .................................................................................... 2-67
Figure 2-56 Basic trigger model ................................................................................................................................... 2-73
Figure 2-57 Advanced trigger model ........................................................................................................................... 2-74
Figure 2-58 External triggering connectors ................................................................................................................. 2-81
Figure 2-59 External triggering and asynchronous trigger link input pulse specifications ......................................... 2-81
Figure 2-60 Meter complete and asynchronous trigger link output pulse specifications ............................................. 2-82
Figure 2-61 DUT test system ....................................................................................................................................... 2-82
Figure 2-62 External trigger connections ..................................................................................................................... 2-82
Figure 2-63 Trigger link connector .............................................................................................................................. 2-84
Figure 2-64 DUT test system ....................................................................................................................................... 2-85
Figure 2-65 Trigger Link connections (asynchronous example #1) ............................................................................ 2-85
Figure 2-66 Operation model for asynchronous trigger link example #1 .................................................................... 2-87
Figure 2-67 Connections using Trigger Link adapter .................................................................................................. 2-88
Figure 2-68 DUT test system (asynchronous example #2) .......................................................................................... 2-88
Figure 2-69 Trigger Link connections (asynchronous example #2) ............................................................................ 2-89
Figure 2-70 Operation model for asynchronous Trigger Link example #2 ................................................................. 2-90
Figure 2-71 Semi-synchronous Trigger Link specifications ........................................................................................ 2-91
Figure 2-72 Typical semi-synchronous mode connections .......................................................................................... 2-91
Figure 2-73 Trigger Link connections (semi-synchronous example) .......................................................................... 2-92
Figure 2-74 Operation model for semi-synchronous Trigger Link example ............................................................... 2-93
Figure 2-75 Digital filter; averaging and advanced filter types ................................................................................. 2-102
Figure 2-76 Digital filter; moving and repeating filter modes ................................................................................... 2-103
Figure 2-77 Limits bar graph example ....................................................................................................................... 2-119
Figure 2-78 Using limit test to sort 100k
Ω
resistors .................................................................................................. 2-120
Figure 2-79 Digital I/O port ....................................................................................................................................... 2-120
Figure 2-80 Digital I/O port simplified schematic ..................................................................................................... 2-121
Figure 2-81 Sample externally powered relays .......................................................................................................... 2-122
Figure 2-82 Line cycle synchronization ..................................................................................................................... 2-123
Figure 2-83 Multiple ground points create a ground loop ......................................................................................... 2-126
Figure 2-84 Eliminating ground loops ....................................................................................................................... 2-127