Intel 80C196KB Series, Руководство пользователя, Страница: 81 / 98

80C196KB USER’S GUIDE
MAXIMUM HOLD LATENCY
The time between HOLD being asserted and HLDA
being driven is known as Hold Latency. After recogniz-
ing HOLD, the 80C196KB waits for any current bus
cycle to finish, and then asserts HLDA. There are 3
types bus cycles; 8-bit external cycle, 16-bit external
cycle,
and an idle bus. Accessing on-chip
ROM/EPROM is an idle bus.
HOLD is an asynchronous input. There are two differ-
ent system configurations for asserting HOLD. The
80C196KB will recognize HOLD internally on the next
clock edge if the system meets Thvch (HOLD valid to
CLKOUT high). If Thvch is not met (HOLD applied
asynchronously), HOLD may be recognized one clock
later (see Figure 15-12). Consult the latest 80C196KB
data sheet for the Thvch specification.
Figure 15-12 shows the 80C196KB entering HOLD
when the bus is idle. This is the minimum hold latency
for both the synchronous and asynchronous cases. If
Thvch is met, HLDA is asserted about on the next
falling edge of CLKOUT. See the data sheet for Tclhal
(CLKOUT low to HLDA low) specification. For this
case, the minimum hold latency
e
Thvcl
a
0.5 states
a
Tclhal.
If HOLD is asserted asynchronously, the minimum
hold latency increases by one state time and
e
Thvcl
a
1.5 states
a
Tclhal.
Figure 15-11 summarizes the additional hold latency
added to the minimum latency for the 3 types of bus
cycles. When accessing external memory, add one state
for each waitstate inserted into the bus cycle. For an
8-bit bus, worst case hold latency is for word reads or
writes. For this case, the bus controller must access the
bus twice, which increases latency by two states.
For exiting Hold, the minimum hold latency times ap-
ply for when the 80C196KB will deassert HLDA in
response to HOLD being removed.
Idle Bus Min
16-bit External Access Min
a
1 state
8-bit External Access Min
a
3 states
Min
e
Thvcl
a
0.5 states
a
Tclhal if Thvcl is met
e
Thvcl
a
1.5 states
a
Tclhal for asynchronous HOLD
Figure 15-11. Maximum Hold Latency
REGAINING BUS CONTROL
There is no delay from the time the 80C196KB re-
moves HLDA to the time it takes control of the bus.
After HOLD is removed, the 80C196KB drops HLDA
in the following state and resumes control of the bus.
BREQ is asserted when the part is in hold and needs to
perform an external memory cycle. An external memo-
ry cycle can be a data access or a request from the
prefetch queue for a code request. A request comes
from the queue when it contains two bytes or less. Once
asserted, it remains asserted until HOLD is removed.
At the earliest, BREQ can be asserted with HLDA.
Hold requests do not freeze the 80C196KB when exe-
cuting out of internal memory. The part continues exe-
cuting as long as the resources it needs are located in-
ternal to the 80C196KB. As soon as the part needs to
access external memory, it asserts BREQ and waits for
the HOLD to be removed. At this time, the part cannot
respond to any interrupt requests until HOLD is re-
moved.
When executing out of external memory during a
HOLD, the 80C196KB keeps running until the queue
is empty or it needs to perform an external data cycle.
The 80C196KB cannot service any interrupts until
HOLD is removed.
The 80C196KB will also respond to hold requests in
the Idle Mode. The latency for entering bus hold from
the Idle Mode is the same as when executing out of
internal memory.
Special consideration must be given to the bus arbiter
design if the 80C196KB can be reset while in HOLD.
For example, a CPU part would try and fetch the CCR
from external memory after RESET is brought high.
Now there would be two parts attempting to access
80C196KB memory. Also, if another bus master is di-
rectly driving ALE, RD, and INST, the ONCE mode
or another test mode could be entered. The simplest
solution is to make the RESET pin of the 80C196KB a
system reset. This way the other bus master would also
be reset. Examples of system reset circuits are given in
Section 13.
77
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