80C196KB USER’S GUIDE
The CPU on the 80C196KB is 16 bits wide and con-
nects to the interrupt controller and the memory con-
troller by a 16-bit bus. In addition, there is an 8-bit bus
which transfers instruction bytes from the memory con-
troller to the CPU. An extension of the 16-bit bus con-
nects the CPU to the peripheral devices.
1.1 Memory Controller
The RALU talks to the memory, except for the loca-
tions in the register file and SFR space, through the
memory controller. Within the memory controller is a
bus controller, a four byte queue and a Slave Program
Counter (Slave PC). Both the internal ROM/EPROM
bus and the external memory bus are driven by the bus
controller. Memory access requests to the bus control-
ler can come from either the RALU or the queue, with
queue accesses having priority. Requests from the
queue are always for instruction at the address in the
slave PC.
By having program fetches from memory referenced to
the slave PC, the processor saves time as addresses sel-
dom have to be sent to the memory controller. If the
address sequence changes because of a jump, interrupt,
call or return, the slave PC is loaded with a new value,
the queue is flushed, and processing continues.
Execution speed is increased by using a queue since it
usually keeps the next instruction byte available. The
instruction execution times shown in Section 3 show
the normal execution times with no wait states added
and the 16-bit bus selected. Reloading the slave PC and
fetching the first byte of the new instruction stream
takes 4 state times. This is reflected in the jump taken/
not-taken times shown in the table.
When debugging code using a logic analyzer, one must
be aware of the queue. It is not possible to determine
when an instruction will begin executing by simply
watching when it is fetched, since the queue is filled in
advance of instruction execution.
1.2 CPU Control
A microcode engine controls the CPU, allowing it to
perform operations with any byte, word or double word
in the 256 byte register space. Instructions to the CPU
are taken from the queue and stored temporarily in the
instruction register. The microcode engine decodes the
instructions and generates the correct sequence of
events to have the RALU perform the desired function.
Figure 1-2 shows the memory controller, RALU, in-
struction register and the control unit.
REGISTER/ALU (RALU)
Most calculations performed by the 80C196KB take
place in the RALU. The RALU, shown in Figure 1-2,
contains a 17-bit ALU, the Program Status Word
(PSW), the Program Counter (PC), a loop counter, and
three temporary registers. All of the registers are 16-
bits or 17-bits (16
a
sign extension) wide. Some of the
registers have the ability to perform simple operations
to off-load the ALU.
A separate incrementor is used for the Program Coun-
ter (PC) as it accesses operands. However, PC changes
due to jumps, calls, returns and interrupts must be han-
dled through the ALU. Two of the temporary registers
have their own shift logic. These registers are used for
the operations which require logical shifts, including
Normalize, Multiply, and Divide. The ‘‘Lower Word’’
and ‘‘Upper Word’’ are used together for the 32-bit
instructions and as temporary registers for many in-
structions. Repetitive shifts are counted by the 6-bit
‘‘Loop Counter’’.
A third temporary register stores the second operand of
two operand instructions. This includes the multiplier
during multiplications and the divisor during divisions.
To perform subtractions, the output of this register can
be complemented before being placed into the ‘‘B’’ in-
put of the ALU.
Several constants, such as 0, 1 and 2 are stored in the
RALU to speed up certain calculations. (e.g. making a
2’s complement number or performing an increment or
decrement instruction.) In addition, single bit masks for
bit test instructions are generated in the constant regis-
ter based on the 3-bit Bit Select register.
1.3 Internal Timing
The 80C196KB requires an input clock on XTAL1 to
function. Since XTAL1 and XTAL2 are the input and
output of an inverter a crystal can be used to generate
the clock. Details of the circuit and suggestions for its
use can be found in Section 13.
Internal operation of the 80C196KB is based on the
crystal or external oscillator frequency divided by 2.
Every 2 oscillator periods is referred to as one ‘‘state
time’’, the basic time measurement for all 80C196KB
operations. With a 12 MHz oscillator, a state time is
167 nanoseconds. With an 8 MHz oscillator, a state
time is 250 nanoseconds, the same as an 8096BH run-
ning with a 12 MHz oscillator. Since the 80C196KB
will be run at many frequencies, the times given
throughout this chapter will be in state times or
‘‘states’’, unless otherwise specified. A clock out
2
数控原理与维修
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Содержание 80C196KB Series
Страница 1: ...November 1990 80C196KB User s Guide Order Number 270651 003 http www agreenleaf cn...
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Страница 60: ...80C196KB USER S GUIDE Figure 11 8 Actual and Ideal Characteristics 270651 38 56 http www agreenleaf cn...
Страница 61: ...80C196KB USER S GUIDE Figure 11 9 Terminal Based Characteristic 270651 39 57 http www agreenleaf cn...
Страница 70: ...80C196KB USER S GUIDE Figure 13 5 Reset Sequence 80C196KB Reset Sequence 270651 45 66 http www agreenleaf cn...
Страница 83: ...80C196KB USER S GUIDE 270651 80 Figure 15 14 AC Timing Diagrams 79 http www agreenleaf cn...
Страница 84: ...80C196KB USER S GUIDE 270651 81 270651 84 Figure 15 14 AC Timing Diagrams Continued 80 http www agreenleaf cn...