Intel 80C196KB Series, Руководство пользователя, Страница: 38 / 98

80C196KB USER’S GUIDE
Figure 6-2. Note that when the PWM register equals
00, the output is always low. Additionally, the PWM
register will only be reloaded from the temporary latch
when the counter overflows. This means the compare
circuit will not recognize a new value until the counter
has expired preventing missed PWM edges.
The 80C196KB PWM unit has a prescaler bit (divide
by 2) which is enabled by setting IOC2.2
e
1. The
PWM frequencies are shown in Figure 6-3. The output
waveform is a variable duty cycle pulse which repeats
every 256 or 512 state times (42.75
m
s or 85.5
m
s at
12 MHz). Changes in the duty cycle are made by writ-
ing to the PWM register at location 17H. The value
programmed into the PWM register can be read in
Window 15 (WSR
e
15). There are several types of mo-
tors which require a PWM waveform for more efficient
operation. Additionally, if this waveform is integrated
it will produce a DC level which can be changed in 256
steps by varying the duty cycle. as described in the next
section.
XTAL1
e
8 MHz 10 MHz 12 MHz
IOC2.2
e
0 15.6 KHz 19.6 KHz 23.6 KHz
IOC2.2
e
1 7.8 KHz 9.8 KHz 11.8 KHz
Figure 6-3. PWM Frequencies
The PWM output shares a pin with Port 2, pin 5 so
that these two features cannot be used at the same time.
IOC1.0 equal to 1 selects the PWM function instead of
the standard port function.
270651 – 12
#
Duty Cycle Programmable in 256 Steps
Figure 6-1. PWM Block Diagram
270651 – 13
Figure 6-2. Typical PWM Outputs
34
数控原理与维修
http://www.agreenleaf.cn