80C196KB USER’S GUIDE
When an HSI event occurs, a 7
c
20 FIFO stores the 16
bits of Timer1, and the 4 bits indicating which pins
recorded events associated with that time tag. There-
fore, if multiple pins are being used as HSI inputs, soft-
ware must check each status bits when processing on
HSI event. Multiple pins can recognize events with the
same time tag. It can take up to 8 state times for this
information to reach the holding register. For this rea-
son, 8 state times must elapse between consecutive
reads of HSIÐTIME. When the FIFO is full, one addi-
tional event, for a total of 8 events, can be stored by
considering the holding register part of the FIFO. If the
FIFO and holding register are full, any additional
events will not be recorded.
8.1 HSI Modes
There are 4 possible modes of operation for each of the
HSI pins. The HSIÐMODE register at location 03H
controls which pins will look for what type of events. In
Window 15, reading the register will read back the pro-
grammed HSI mode. The 8-bit register is set up as
shown in Figure 8-3.
270651 – 20
Figure 8-3. HSI Mode Register 1
The maximum input speed is 1 event every 8 state times
except when the 8 transition mode is used, in which
case it is 1 transition per state time.
The HSI pins can be individually enabled and disabled
using bits in IOC0 as shown in Figure 8-4. If the pin is
disabled, transitions are not entered in the FIFO. How-
ever, the input bits of the HSIÐSTATUS register (Fig-
ure 8-2) are always valid regardless of whether the pin
is enabled to the FIFO. This allows the HSI pins to be
used as general purpose input pins.
270651 – 21
Figure 8-4. IOC0 Control of HSI Pin Functions
8.2 HSI Status
Bits 6 and 7 of the I/O Status Register 1 (IOS1Ðsee
Figure 8-5) indicate the status of the HSI FIFO. If bit 7
is set, the HSI holding register is loaded. The FIFO
may or may not contain 1 – 5 events. If bit 6 is set, the
FIFO contains 6 entries. If the FIFO fills, future events
will not be recorded. Reading IOS1 clears bits 0 – 5, so
keep an image of the register and test the image to
retain all 6 bits.
Reading the HSI holding register must be done in a
certain order. The HSIÐSTATUS Register (Figure 8-
2) is read first to obtain the status and input bits. Sec-
ond, the HSIÐTIME Register (04H) is read to obtain
the time tag. Reading HSIÐTIME unloads one level of
the
FIFO.
If
the
HSIÐTIME is read before
HSIÐSTATUS, the contents of HSIÐSTATUS associ-
ated with that HSIÐTIME tag are lost.
270651 – 23
Figure 8-5. I/O Status Register 1
39
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Содержание 80C196KB Series
Страница 1: ...November 1990 80C196KB User s Guide Order Number 270651 003 http www agreenleaf cn...
Страница 59: ...80C196KB USER S GUIDE Figure 11 7 Ideal A D Characteristic 270651 37 55 http www agreenleaf cn...
Страница 60: ...80C196KB USER S GUIDE Figure 11 8 Actual and Ideal Characteristics 270651 38 56 http www agreenleaf cn...
Страница 61: ...80C196KB USER S GUIDE Figure 11 9 Terminal Based Characteristic 270651 39 57 http www agreenleaf cn...
Страница 70: ...80C196KB USER S GUIDE Figure 13 5 Reset Sequence 80C196KB Reset Sequence 270651 45 66 http www agreenleaf cn...
Страница 83: ...80C196KB USER S GUIDE 270651 80 Figure 15 14 AC Timing Diagrams 79 http www agreenleaf cn...
Страница 84: ...80C196KB USER S GUIDE 270651 81 270651 84 Figure 15 14 AC Timing Diagrams Continued 80 http www agreenleaf cn...