Intel 80C196KB Series, Руководство пользователя, Страница: 12 / 98

80C196KB USER’S GUIDE
Within the SFR space are several registers and bit loca-
tions labeled ‘‘RESERVED’’. These locations should
never be written or read. A reserved bit location should
always be written with 0 to maintain compatibility with
future parts. Values read from these locations may
change from part to part or over temperature and volt-
age. Registers and bits which are not labeled should be
treated as reserved registers and bits. Note that the de-
fault state of internal registers is 0, while that for exter-
nal memory is 1. This is because SFR functions are
typically disabled with a zero, while external memory is
typically erased to all 1s.
Caution must be taken when using the SFRs as sources
of operations or as base or index registers for indirect or
indexed operations. It is possible to get undesired re-
sults, since external events can change SFRs and some
SFRs clear when read. The potential for an SFR to
change value must be taken into account when operat-
ing on these registers. This is particularly important
when high level languages are used as they may not
always make allowances for SFR-type registers. SFRs
can be operated on as bytes or words unless otherwise
specified.
2.3 Reserved Memory Spaces
Locations 1FFEH and 1FFFH are used for Ports 3 and
4 respectively, allowing easy reconstruction of these
ports if external memory is used. An example of recon-
structing the I/O ports is given in Section 15. If ports 3
and 4 are not going to be reconstructed and internal
ROM/EPROM is not used, these locations can be
treated as any other external memory location.
Many reserved and special locations are in the memory
area between 2000H and 2080H. In this area the 18
interrupt vectors, chip configuration byte, and security
key are located. Figure 2-6 shows the locations and
functions of these registers. The interrupts, chip config-
uration, and security key registers are discussed in Sec-
tions 5, 16, and 17 respectively. With one exception, all
unspecified addresses in locations 2000H through
207FH, including those marked ‘‘Reserved’’ are re-
served by Intel for use in testing or future products.
They must be filled with the Hex value FFH to insure
compatibility with future devices. Location 2019H
should contain 20H to prevent possible bus contention
during the CCB fetch cycle. NOTE: 1. This exception
applies only to systems with a 16-bit bus and external
program memory. 2. Previously designed systems
which do not experience bus contention don’t need to
change the contents of this location. Refer to Section
15.2 for more information about bus contention during
CCB fetch.
FFFFH
EXTERNAL MEMORY
OR I/O
4000H
INTERNAL PROGRAM
STORAGE ROM/EPROM
OR
EXTERNAL MEMORY 2080H
RESERVED 2074H–207FH
VOLTAGE LEVELS 2072H–2073H
SIGNATURE WORD 2070H–2071H
RESERVED 2040H–206FH
INTERRUPT VECTORS 2030H–203FH
SECURITY KEY 2020H–202FH
RESERVED 2019H–201FH
CHIP CONFIGURATION BYTE 2018H
RESERVED 2015H–2017H
PPW 2014H
INTERRUPT VECTORS 2000H–2013H
Figure 2-6. Reserved Memory Spaces
Resetting the 80C196KB causes instructions to be
fetched starting from location 2080H. This location was
chosen to allow a system to have up to 8K of RAM
continuous with the register file. Further information
on reset can be found in Section 13.
2.4 Internal ROM and EPROM
When a ROM part is ordered, or an EPROM part is
programmed, the internal memory locations 2080H
through 3FFFH are user specified, as are the interrupt
vectors, Chip Configuration Register and Security Key
in locations 2000H through 207FH. Location 2014H
contains the PPW (Programming Pulse Width) regis-
ter. The PPW is used solely to program 87C196KB
EPROM devices and is a reserved location on ROM
and ROMless devices.
Instruction and data fetches from the internal ROM or
EPROM occur only if the part has ROM or EPROM,
EA is tied high, and the address is between 2000H and
3FFFH. At all other times data is accessed from either
the internal RAM space or external memory and in-
structions are fetched from external memory. The EA
pin is latched on RESET rising. Information on pro-
gramming EPROMs can be found in Section 16.
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