Intel 80C196KB Series, Руководство пользователя, Страница: 21 / 98

80C196KB USER’S GUIDE
Table 3-1C. Instruction Summary
Mnemonic Operands Operation (Note 1)
Flags
Notes
Z N C V VT ST
CLRVT 0 VT
w
0
b b b b
0
b
RST 0 PC w 2080H 0 0 0 0 0 0 8
DI 0 Disable All Interupts (I w 0)
b b b b b b
EI 0 Enable All Interupts (I
w
1)
b b b b b b
NOP 0 PC
w
PC
a
1
b b b b b b
SKIP 0 PC
w
PC
a
2
b b b b b b
NORML 2 Left shift till msb
e
1; D
w
shift count
& &
0
b b b
7
TRAP 0 SP
w
SP
b
2;
b b b b b b
9
(SP)
w
PC; PC
w
(2010H)
PUSHA 1 SP
w
SP-2; (SP)
w
PSW; 0 0 0 0 0 0
PSW
w
0000H; SP
w
SP-2;
(SP)
w
IMASK1/WSR; IMASK1
w
00H
POPA 1 IMASK1/WSR
w
(SP); SP
w
SP
a
2
& & & & & &
PSW
w
(SP); SP
w
SP
a
2
IDLPD 1 IDLE MODE IF KEY
e
1;
b b b b b b
POWERDOWN MODE IF KEY
e
2;
CHIP RESET OTHERWISE
CMPL 2 D-A
& & & &
u
b
BMOV 2 [ PTRÐHI ]
a
w
[ PTRÐLOW ]
a
;
b b b b b b
UNTIL COUNT
e
0
NOTES:
1. If the mnemonic ends in ‘‘B’’ a byte operation is performed, otherwise a word operation is done. Operands D, B, and A
must conform to the alignment rules for the required operand type. D and B are locations in the Register File; A can be
located anywhere in memory.
2. D,D
a
2 are consecutive WORDS in memory; D is DOUBLE-WORD aligned.
3. D,D
a
1 are consecutive BYTES in memory; D is WORD aligned.
4. Changes a byte to word.
5. Offset is a 2’s complement number.
6. Specified bit is one of the 2048 bits in the register file.
7. The ‘‘L’’ (Long) suffix indicates double-word operation.
8. Initiates a Reset by pulling RESET low. Software should re-initialize all the necessary registers with code starting at
2080H.
9. The assembler will not accept this mnemonic.
10. The DJNZW instruction is not guaranteed to work. See Functional Deviations section.
17
数控原理与维修
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