Intel 80C196KB Series, Руководство пользователя, Страница: 18 / 98

80C196KB USER’S GUIDE
INTERRUPT FLAGS
The lower eight bits of the PSW individually mask the
lowest 8 sources of interrupt to the 80C196KB. These
mask bits can be accessed as an eight bit byte (INTÐ
MASKÐaddress 8) in the on-board register file. A sep-
arate register (INTÐMASK1Ðaddress 13H) contains
the control bits for the higher 8 interrupts. A logical ‘1’
in these bit positions enables the servicing of the corre-
sponding interrupt. Bit 9 in the PSW is the global inter-
rupt disable. If this bit is cleared then interrupts will be
locked out. Note that the interrupts are collected in the
INTÐPEND registers even if they are locked out. Exe-
cution of the corresponding service routines will pro-
ceed according to their priority when they become en-
abled. Further information on the interrupt structure of
the 80C196KB can be found in Section 5.
3.4 Instruction Set
The MCS-96 instruction set contains a full set of arith-
metic and logical operations for the 8-bit data types
BYTE and SHORT INTEGER and for the 16-bit data
types WORD and INTEGER. The DOUBLE-WORD
and LONG data types (32 bits) are supported for the
products of 16-by-16 multiplies and the dividends of
32-by-16 divides, for shift operations, and for 32-bit
compares. The remaining operations on 32-bit variables
can be implemented by combinations of 16-bit opera-
tions. As an example the sequence:
ADD AX,CX
ADDC BX,DX
performs a 32-bit addition, and the sequence
SUB AX,CX
SUBC BX,DX
performs a 32-bit subtraction. Operations on REAL
(i.e. floating point) variables are not supported directly
by the hardware but are supported by the floating point
library for the 80C196KB (FPAL-96) which imple-
ments a single precision subset of draft 10 of the IEEE
standard for floating point arithmetic. The performance
of this software is significantly improved by the
80C196KB NORML instruction which normalizes a
32-bit variable and by the existence of the ST flag in the
PSW.
In addition to the operations on the various data types,
the 80C196KB supports conversions between these
types. LDBZE (load byte zero extended) converts a
BYTE to a WORD and LDBSE (load byte sign extend-
ed) converts a SHORT-INTEGER into an INTEGER.
WORDS can be converted to DOUBLE-WORDS by
simply clearing the upper WORD of the DOUBLE-
WORD (CLR) and INTEGERS can be converted to
LONGS with the EXT (sign extend) instruction.
The MCS-96 instructions for addition, subtraction, and
comparison do not distinguish between unsigned words
and signed integers. Conditional jumps are provided to
allow the user to treat the results of these operations as
either signed or unsigned quantities. As an example, the
CMPB (compare byte) instruction is used to compare
both signed and unsigned eight bit quantities. A JH
(jump if higher) could be used following the compare if
unsigned operands were involved or a JGT (jump if
greater-than) if signed operands were involved.
Tables 3-1 and 3-2 summarize the operation of each of
the instructions. Complete descriptions of each instruc-
tion and its timings can be found in the MCS-96 family
Instruction Set chapter.
The execution times for the instruction set are given in
Figure 3-3. These times are given for a 16-bit bus with
no wait states. On-chip EPROM/ROM space is a 16-
bit, zero wait state bus. When executing from an 8-bit
external memory system or adding wait states, the CPU
becomes bus limited and must sometimes wait for the
prefetch queue. The performance penalty for an 8-bit
external bus is difficult to measure, but has shown to be
between 10 and 30 percent based on the instruction
mix. The best way to measure code performance is to
actually benchmark the code and time it using an emu-
lator or with TIMER1.
The indirect and indexed instruction timings are given
for two memory spaces: SFR/Internal RAM space (0 –
0FFH), and a memory controller reference (100H –
0FFFFH). Any instruction that uses an operand that is
referenced through the memory controller (ex. Add
r1,5000H
[
0
]
) takes 2 – 3 states longer than if the oper-
and was in the SFR/Internal RAM space. Any data
access to on-chip ROM/EPROM is considered to be a
memory controller reference.
Flag Settings.
The modification to the flag setting is
shown for each instruction. A checkmark (
&
) means
that the flag is set or cleared as appropriate. A hyphen
means that the flag is not modified. A one or zero (1) or
(0) indicates that the flag will be in that state after the
instruction. An up arrow (
u
) indicates that the in-
struction may set the flag if it is appropriate but will
not clear the flag. A down arrow (
v
) indicates that the
flag can be cleared but not set by the instruction. A
question mark (?) indicates that the flag will be left in
an indeterminant state after the operation.
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