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80C196KB USER’S GUIDE

MODE 2

Mode 2 is the asynchronous 9th bit recognition mode.
This mode is commonly used with Mode 3 for multi-
processor communications. Figure 10-4 shows the data
frame used in this mode. It consists of a start bit (0), 9
data bits (LSB first), and a stop bit (1). When transmit-
ting, the 9th bit can be set to a one by setting the TB8
bit in the control register before writing to SBUF (TX).
The TB8 bit is cleared on every transmission, so it must
be set prior to writing to SBUF (TX). During recep-
tion, the serial port interrupt and the Receive Interrupt
will not occur unless the 9th bit being received is set.
This provides an easy way to have selective reception
on a data link. Parity cannot be enabled in this mode.

MODE 3

Mode 3 is the asynchronous 9th bit mode. The data
frame for this mode is identical to that of Mode 2. The
transmission differences between Mode 3 and Mode 2
are that parity can be enabled (PEN

e

1) and cause the

9th data bit to take the even parity value. The TB8 bit
can still be used if parity is not enabled (PEN

e

0).

When in Mode 3, a reception always causes an inter-
rupt, regardless of the state of the 9th bit. The 9th bit is
stored if PEN

e

0 and can be read in bit RB8. If

PEN

e

1 then RB8 becomes the Receive Parity Error

(RPE) flag.

Mode 2 and 3 Timings

Modes 2 and 3 operate in a manner similar to that of
Mode 1. The only difference is that the data is now
made up of 9 bits, so 11-bit packages are transmitted
and received. This means that TI and RI will be set on
the 9th data bit rather than the 8th. The 9th bit can be
used for parity or multiple processor communications.

10.4 Multiprocessor Communications

Mode 2 and 3 are provided for multiprocessor commu-
nications. In Mode 2 if the received 9th data bit is zero,
the RI bit is not set and will not cause an interrupt. In
Mode 3, the RI bit is set and always causes an interrupt
regardless of the value in the 9th bit. The way to use
this feature in multiprocessor systems is described be-
low.

The master processor is set to Mode 3 so it always gets
interrupts from serial receptions. The slaves are set in
Mode 2 so they only have receive interrupts if the 9th

bit is set. Two types of frames are used: address frames
which have the 9th bit set and data frames which have
the 9th bit cleared. When the master processor wants to
transmit a block of data to one of several slaves, it first
sends out an address frame which identifies the target
slave. Slaves in Mode 2 will not be interrupted by a data
frame, but an address frame will interrupt all slaves.
Each slave can examine the received byte and see if it is
being addressed. The addressed slave switches to Mode
3 to receive the coming data frames, while the slaves
that were not addressed stay in Mode 2 continue exe-
cuting.

11.0 A/D CONVERTER

Analog Inputs to the 80C196KB System are handled
by the A/D converter System. As shown in Figure
11-4, the converter system has an 8 channel multiplex-
er, a sample-and-hold, and a 10 bit successive approxi-
mation A/D converter. Conversions can be performed
on one of eight channels, the inputs of which share pins
with port 0. A conversion can be done in as little as 91
state times.

Conversions are started by loading the ADÐCOM-

MAND register at location 02H with the channel num-
ber. The conversion can be started immediately by set-
ting the GO bit to a one. If it is cleared the conversion
will start when the HSO unit triggers it. The A/D com-
mand register must be written to for each conversion,
even if the HSO is used as the trigger. The result of
the conversion is read in the ADÐRESULT(High)

and ADÐRESULT(Low) registers. The ADÐRE-

SULT(High) contains the most significant eight bits of
the conversion. The ADÐRESULT(Low) register con-

tains the remaining two bits and the A/D channel num-
ber and A/D status. The format for the ADÐCOM-

MAND register is shown in Figure 11-1. In Window
15, reading the ADÐCOMMAND register will read

the last command written. Writing to the ADÐRE-

SULT register will write a value into the result register.

270651 – 33

Figure 11-1. A/D Command Register

51

数控原理与维修 

http://www.agreenleaf.cn

Содержание 80C196KB Series

Страница 1: ...November 1990 80C196KB User s Guide Order Number 270651 003 http www agreenleaf cn...

Страница 2: ...any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and p...

Страница 3: ...ontrol 29 5 2 Interrupt Priorities 29 5 3 Critical Regions 31 5 4 Interrupt Timing 31 5 5 Interrupt Summary 32 CONTENTS PAGE 6 0 Pulse Width Modulation Output D A 33 6 1 Analog Outputs 35 7 0 TIMERS 3...

Страница 4: ...69 14 3 ONCE and Test Modes 70 CONTENTS PAGE 15 0 EXTERNAL MEMORY INTERFACING 71 15 1 Bus Operation 71 15 2 Chip Configuration Register 72 15 3 Bus Width 75 15 4 HOLD HLDA Protocol 76 15 5 AC Timing E...

Страница 5: ...e controls photocopiers anti lock brakes air conditioner temperature controls disk drives and medical instrumentation There are many members of the 80C196KB family so to provide easier reading this ma...

Страница 6: ...re 1 2 shows the memory controller RALU in struction register and the control unit REGISTER ALU RALU Most calculations performed by the 80C196KB take place in the RALU The RALU shown in Figure 1 2 con...

Страница 7: ...80C196KB USER S GUIDE Figure 1 2 RALU and Memory Controller Block Diagram 270651 2 3 http www agreenleaf cn master PC...

Страница 8: ...be accessed as bytes 8 bits words 16 bits or double words 32 bits Since each of these locations can be used by the RALU there are essential ly 232 accumulators This memory region as well as the status...

Страница 9: ...N 10H PORT2 10H PORT2 10H RESERVED 0FH PORT1 0FH PORT1 0FH RESERVED 0EH PORT0 0EH BAUD RATE 0EH RESERVED 0DH TIMER2 HI 0DH TIMER2 HI 0DH T2 CAPTURE HI 0CH TIMER2 LO 0CH TIMER2 LO 0CH T2 CAPTURE LO 0BH...

Страница 10: ...Written periodically to hold off automatic reset every 64K state times Returns upper byte of WDT counter in Window 15 TIMER1 Timer 1 Hi Lo Timer1 high and low bytes TIMER2 Timer 2 Hi Lo Timer2 high an...

Страница 11: ...ing register SBUF RX 07H Write a value into the receive buffer SBUF TX 07H Read the last value written to the transmit buffer WATCHDOG 0AH Read the value in the upper byte of the WDT TIMER1 0AH 0BH Wr...

Страница 12: ...ception all unspecified addresses in locations 2000H through 207FH including those marked Reserved are re served by Intel for use in testing or future products They must be filled with the Hex value F...

Страница 13: ...CX DL is the low byte of DX These are the same as the names for the general data registers used in the 8086 It is important to note that in the 80C196KB these are not dedicated registers but merely th...

Страница 14: ...rchitecture provides di rect support for this data type for shifts as the dividend in a 32 by 16 divide and the product of a 16 by 16 mul tiply and for double word comparisons LONG INTEGERS can also b...

Страница 15: ...xamples LD AX BX 0 AX 4MEM WORD BX BX 4BX02 ADDB AL BL CX 0 AL 4BL0MEM BYTE CX CX 4CX01 PUSH AX 0 SP 4SP12 MEM WORD SP 4MEM WORD AX AX 4AX02 IMMEDIATE REFERENCES This addressing mode allows an operand...

Страница 16: ...on the stack pointer can be used in the short indexed mode to access data within the stack Examples PUSH SP DUPLICATE TOP OF STACK LD AX 2 SP AX 4NEXT TO TOP ASSEMBLY LANGUAGE ADDRESSING MODES The MCS...

Страница 17: ...the testing for a possible overflow con dition at the end of a sequence of related arithme tic operations This is normally more efficient than testing the V flag after each instruction C The Carry fl...

Страница 18: ...OUBLE WORD CLR and INTEGERS can be converted to LONGS with the EXT sign extend instruction The MCS 96 instructions for addition subtraction and comparison do not distinguish between unsigned words and...

Страница 19: ...a 2 A D a 2 w remainder b b b u b DIVB 2 D w D D a 1 A D a 1 w remainder b b b u b AND ANDB 2 D w D AND A 0 0 b b AND ANDB 3 D w B AND A 0 0 b b OR ORB 2 D w D OR A 0 0 b b XOR XORB 2 D w D ecxl or A...

Страница 20: ...if V e 1 b b b b b b 5 JNV 1 Jump if V e 0 b b b b b b 5 JVT 1 Jump if VTe 1 Clear VT b b b b 0 b 5 JNVT 1 Jump if VT e 0 Clear VT b b b b 0 b 5 JST 1 Jump if ST e 1 b b b b b b 5 JNST 1 Jump if ST e...

Страница 21: ...a w PTR LOW a b b b b b b UNTIL COUNTe0 NOTES 1 If the mnemonic ends in B a byte operation is performed otherwise a word operation is done Operands D B and A must conform to the alignment rules for th...

Страница 22: ...op 3 6C 4 6D 3 6E 3 6E 4 6F 5 6F DIV 4 2 5 2 4 2 4 2 5 2 6 2 DIVU 3 8C 4 8D 3 8E 3 8E 4 8F 5 8F MULB 3 op 5 2 5 2 5 2 5 2 6 2 7 2 MULUB 3 op 4 5C 4 5D 4 5E 4 5E 5 5F 6 5F MULB 2 op 4 2 4 2 4 2 4 2 5...

Страница 23: ...27 3 BR 2 E3 JNST 1 D0 JST 1 D8 JNH 1 D1 JH 1 D9 JGT 1 D2 JLE 1 DA JNC 1 B3 JC 1 D8 JNVT 1 D4 JVT 1 DC JNV 1 D5 JV 1 DD JGE 1 D6 JLT 1 DE JNE 1 D7 JE 1 DF JBC 3 30 37 JBS 3 38 3F Mnemonic Length Opco...

Страница 24: ...17 15 18 15 18 16 19 MULUB 2 op 10 10 12 15 13 15 12 16 14 17 DIVB 18 18 20 23 21 24 21 24 22 25 DIVUB 16 16 18 21 19 22 19 22 20 23 AND 3 op 5 6 7 10 8 11 7 10 8 11 AND 2 op 4 5 6 8 7 9 6 8 7 9 OR 2...

Страница 25: ...4 8 jump not taken jump taken JNVT JVT 4 8 jump not taken jump taken JNV JV 4 8 jump not taken jump taken JGE JLT 4 8 jump not taken jump taken JNE JE 4 8 jump not taken jump taken JBC JBS 5 9 jump n...

Страница 26: ...ery usable standard for both the assembly language and PLM 96 environment and it offers com patibility between these environments Another advan tage is that it allows the user access to the same float...

Страница 27: ...with NOPs and periodic jumps to an error routine or RST reset chip instructions This is particularly im portant in the code around lookup tables since if look up tables are executed undesired results...

Страница 28: ...Data is taken off the FIFO by reading the HSI STATUS register followed by reading the HSI TIME register When the time register is read the next FIFO location is loaded into the holding regis ter Thre...

Страница 29: ...igger Options 270651 18 270651 19 Figure 4 3 HSI Block Diagram HIGH SPEED OUTPUT CONTROLS 6 PINS 4 SOFTWARE TIMERS 2 INTERRUPTS INITIATE A D CONVERSION RESET TIMER2 270651 8 Figure 4 4 HSO Block Diagr...

Страница 30: ...D conversion is performed on one input at a time using successive approximation with a result equal to the ratio of the input voltage divided by the analog supply voltage If the ratio is 1 00 then the...

Страница 31: ...hich enable some of the sources Special Interrupts Three special interrupts are available on the 80C196KB NMI TRAP and Unimplemented opcode The external NMI pin generates an unmaskable inter rupt for...

Страница 32: ...rs The TRAP instruc tion prevents the acknowledgement of interrupts until after execution of the next instruction Unimplemented Opcode Opcodes which are not implemented on the 80C196KB will cause an i...

Страница 33: ...same as that of the Inter rupt Pending Register shown in Figure 5 3 The INT MASK and INT MASK1 registers can be read or written as byte registers A one in any bit posi tion will enable the correspondi...

Страница 34: ...n interesting chain of instruction side effects which makes this or any other 80C196KB interrupt service routine execute properly A After the interrupt controller decides to process an interrupt it ex...

Страница 35: ...ust be made as a single in struction since bits can be changed in this register even if interrupts are disabled Depending on system config urations several other SFRs might also need to be changed in...

Страница 36: ...I followed immediately by a long instruction e g MUL NORML etc will in crease the maximum latency by 4 state times as an interrupt cannot occur between EI and the instruction following EI The DI PUSHF...

Страница 37: ...pts shared the same interrupt vector TIMER OVERFLOW 2000H on the 8096BH The interrupts are individually enabled by setting bits 2 and 3 of IOC1 bit 2 for Timer1 and bit 3 for Timer2 Which timer actual...

Страница 38: ...ng to the PWM register at location 17H The value programmed into the PWM register can be read in Window 15 WSRe15 There are several types of mo tors which require a PWM waveform for more efficient ope...

Страница 39: ...and power supply drift a highly accurate 8 bit D to A converter can be made using either the HSO or the PWM output Figure 6 5 shows two typical circuits If the HSO is used the accuracy could be theor...

Страница 40: ...y in one direction High Speed Output events based on Timer2 must be carefully programmed when using Timer2 as an up down counter or is reset externally Programmed events could be missed or occur in th...

Страница 41: ...651 17 Figure 7 3 Timer2 Clock and Reset Options 7 4 Timer Interrupts Both Timer1 and Timer2 can trigger a timer overflow interrupt and set a flag in the I O Status Register 1 IOS1 Timer1 overflow is...

Страница 42: ...but not cause interrupts The general enabling and disabling of the timer interrupts are controlled by the Interrupt Mask Register bit 0 In all cases setting a bit enables a func tion while clearing a...

Страница 43: ...the 8 transition mode is used in which case it is 1 transition per state time The HSI pins can be individually enabled and disabled using bits in IOC0 as shown in Figure 8 4 If the pin is disabled tr...

Страница 44: ...FO independent of the holding register The interrupt is enabled by setting INT MASK1 2 The HSI FIFO 4 vectors indirectly through location 2034H There is no status flag associated with the HSI FIFO 4 i...

Страница 45: ...High Speed Output execution interrupt can be generat ed if enabled for HSO commands which change one or more of the six output pins The other HSO inter rupt is the interrupt which can be generated by...

Страница 46: ...ram of the HSO unit is shown in Figure 9 3 The Content Addressable Memory CAM file is the center of control One CAM register is compared with the timer values every state time taking 8 state times to...

Страница 47: ...ing register is empty and at least one CAM register is emp ty If IOS0 7 equals 0 the holding register is empty The programmer should carefully decide which of these two flags is the best to use for ea...

Страница 48: ...nd the comparator has a chance to look at all 8 CAM registers before Timer1 changes its value Writ ing to Timer1 which is allowed in Window 15 should be carefully done The user should ensure writing t...

Страница 49: ...has one synchronous and 3 asynchronous modes The asynchronous modes include reg196 inc GENERATION OF FOUR PWM S USING LOCKED ENTRIES Timer2 is used as a reference and is clocked externally by T2CLK T...

Страница 50: ...e PWM period set hso high on t2rst nop nop nop nop ldb hso command 0c0h set HSO 0 low locked timer2 as reference ld hso time pwm0timl HSO 0 time low nop nop nop nop ldb hso command 0c1h set HSO 1 low...

Страница 51: ...the Transmit Interrupt TI bit the Receive Interrupt RI bit and the Received Bit 8 RB8 or Receive Parity Error RPE bit SP STAT is read only in Window 0 and is shown in Figure 10 1 In all modes the RI...

Страница 52: ...pproximately in the middle of the bit time Also for all modes the TI flag is set after the last data bit either 8th or 9th is sent also in the middle of the bit time The flags clear when SP STAT is re...

Страница 53: ...nt in the number of bytes being transmitted 10 3 Serial Port Modes MODE 0 Mode 0 is a synchronous mode which is commonly used for shift register based I O expansion In this mode the TXD pin outputs a...

Страница 54: ...ions are com plete TI is set when the last data bit of the message has been sent not when the stop bit is sent If an attempt to send another byte is made before the stop bit is sent the port will hold...

Страница 55: ...processor systems is described be low The master processor is set to Mode 3 so it always gets interrupts from serial receptions The slaves are set in Mode 2 so they only have receive interrupts if the...

Страница 56: ...nt 8 bits of the conversion The lower byte format is shown in Figure 11 2 At high crystal frequencies more time is needed to al low the comparator to settle For this reason IOC2 4 is provided to adjus...

Страница 57: ...sted This corresponds to a 10 bit result where the most significant bit is zero and all other bits are ones 0111 1111 11b If the ana log input was less than the test voltage bit 10 of the SAR is left...

Страница 58: ...I O 11 3 The A D Transfer Function The conversion result is a 10 bit ratiometric representa tion of the input voltage so the numerical value ob tained from the conversion will be INT 1023 c VIN b ANGN...

Страница 59: ...80C196KB USER S GUIDE Figure 11 7 Ideal A D Characteristic 270651 37 55 http www agreenleaf cn...

Страница 60: ...80C196KB USER S GUIDE Figure 11 8 Actual and Ideal Characteristics 270651 38 56 http www agreenleaf cn...

Страница 61: ...80C196KB USER S GUIDE Figure 11 9 Terminal Based Characteristic 270651 39 57 http www agreenleaf cn...

Страница 62: ...ed and trimmed within the specified range to affect full scale error Other factors that affect a real A D Converter system include sensitivity to temperature failure to completely reject all unwanted...

Страница 63: ...The maximum deviation of code transitions of the terminal based characteristic from the corresponding code transitions of the ideal characteris tics OFF ISOLATION Attenuation of a voltage applied on a...

Страница 64: ...t drivers on these pins The input leakage of these pins is in the microamp range The specific values can be found in the data sheet for the device being consid ered Figure 12 2 shows the input port st...

Страница 65: ...tional port Outputting a 0 on a quasi bidirectional pin turns on the strong pull down and turns off all of the pull ups When a 1 is output the pull down is turned off and 3 pull ups strong P1 weak P3...

Страница 66: ...series resistor between the port pin and the base of the transistor often works by bringing up the voltage present on the port pin The second case can be taken care of in the software fairly easily L...

Страница 67: ...first setup the input port configura tion circuit Note that the ports are reset to this input condition but if zeroes have been written to the port then ones must be re written to any pins which are...

Страница 68: ...pins VSS1 VSS2 VSS3 and Angd must all be nominally at 0 volts Even if the A D converter is not being used VREF and Angd must still be connected for Port0 to function 13 2 Noise Protection Tips Due to...

Страница 69: ...his over view will be in state times Two non overlapping internal phases are created by the clock generator phase 1 and phase 2 as shown in Fig ure 13 4 CLKOUT is generated by the rising edge of phase...

Страница 70: ...80C196KB USER S GUIDE Figure 13 5 Reset Sequence 80C196KB Reset Sequence 270651 45 66 http www agreenleaf cn...

Страница 71: ...ned Input READY Undefined Input NMI Undefined Input BUSWIDTH Undefined Input CLKOUT Phase 2 of Clock System Bus P3 0 P4 7 Weak Pullups ACH0 7 P0 0 P0 7 Undefined Input PORT1 P1 0 P1 7 Weak Pullups TXD...

Страница 72: ...e RESET is only asserted for four state times If this is done it is possible for the 80C196KB to start running before oth er chips in the system are out of reset Software must take this condition into...

Страница 73: ...herals are running the interrupt can be generated by the HSI HSO A D serial port etc When an interrupt brings the CPU out of the Idle Mode the CPU vectors to the corresponding interrupt service routin...

Страница 74: ...ately 100 uA When the voltage goes below about 1 volt on the VPP pin the chip begins executing code A 1uF capacitor would take about 4 ms to discharge to 1 volt If the external interrupt brings the ch...

Страница 75: ...latches 74AC373s to demultiplex the bus To avoid confusion the latched address signals will be called MA0 MA15 and the data signals will be named MD0 MD15 The data returned from external memory must...

Страница 76: ...her internal or external memory depending on the state of the EA pin The CCR is only written once during the reset sequence Once loaded the CCR cannot be changed until the next reset The CCR is shown...

Страница 77: ...Using the CCR the 80C196KB can generate several types of control signals designed to reduce external hardware The ALE WR and BHE pins serve dual functions Bits 2 and 3 of the CCR specify the function...

Страница 78: ...ess Valid Strobe Mode Address Valid strobe replaces ALE if CCR bit 3 is 0 When Address valid Strobe mode is selected ADV will be asserted after an external address is setup It will stay asserted until...

Страница 79: ...ltiplexed with data using ALE to latch the address In 8 bit bus cycles Port 3 is multiplexed with address data but Port 4 only outputs the upper 8 ad dress bits The Addresses on Port 4 are valid throu...

Страница 80: ...otocol consists of three signals HOLD HLDA and BREQ HOLD is an input asserted by a device which requests the 80C196KB bus Figure 15 10 shows the timing for HOLD HLDA The 80C196KB responds by releasing...

Страница 81: ...l if Thvcl is met e Thvcl a 1 5 states a Tclhal for asynchronous HOLD Figure 15 11 Maximum Hold Latency REGAINING BUS CONTROL There is no delay from the time the 80C196KB re moves HLDA to the time it...

Страница 82: ...the block that needs to be protect ed from HOLD requests The safest way is to add a JBC instruction to check the status of the HLDA pin after the code that clears the HLDEN bit Figure 15 13 is an exam...

Страница 83: ...80C196KB USER S GUIDE 270651 80 Figure 15 14 AC Timing Diagrams 79 http www agreenleaf cn...

Страница 84: ...80C196KB USER S GUIDE 270651 81 270651 84 Figure 15 14 AC Timing Diagrams Continued 80 http www agreenleaf cn...

Страница 85: ...ess TRLDV RD Low to Input Data Valid Maximum time the memory system has to output valid data after the 80C196KB asserts RD TCLDV CLKOUT Low to Input Data Valid Maximum time the memory system has to ou...

Страница 86: ...ec TCHWH CLKOUT High to WR Rising Edge Time between CLKOUT going high and WR going inactive Useful in systems based on CLKOUT TWLWH WR Low to WR High WR pulse width Memory devices must meet this spec...

Страница 87: ...M and RAM is shown in Figure 15 17 The EPROM is decod ed in the lower half of memory and the RAM in the upper half Figure 15 18 shows a 16 bit system with 2 EPROMs Again ADV is used to chip select the...

Страница 88: ...80C196KB USER S GUIDE 270651 69 Figure 15 19 16 Bit System with Dynamic Buswidth 270651 70 Figure 15 20 I O Port Reconstruction 84 http www agreenleaf cn...

Страница 89: ...amming Mode enables an 87C196KB to program itself without using an EPROM programmer The Slave Programming Mode provides a standard interface for programming any number of 87C196KB s by a master device...

Страница 90: ...1 2 4V minimum 2 The same power supply can be used for EA and VPP However the EA pin must be powered up before VPP is powered up Also EA should be protected from noise to prevent damage to it 3 Exceed...

Страница 91: ...rogramming Rising edge indicates end of programming P2 0 PVER Program Verification Output Low signal after rising edge of PROG indicates programming was not successful P2 4 AINC Auto Increment Input A...

Страница 92: ...d the CCR will be load ed with 0FFFH when the device is in the Programming Mode 16 5 Auto Programming Mode The Auto Programming Mode provides the ability to program the 87C196KB EPROM without using an...

Страница 93: ...80C196KB USER S GUIDE 270651 72 NOTES Inputs must be driven high or low Allow RESET to rise after the voltages to VCC EA and VPP are stable Figure 16 4 Auto Programming Mode 89 http www agreenleaf cn...

Страница 94: ...KB receives an input signal PALE to in dicate a valid command is present PROG causes the 87C196KB to read in or output a data word PVER indicates if the programming was successful AINC au tomatically...

Страница 95: ...rd Dump Command When the Word Dump Command is issued the 87C196KB adds 2000H to the address field of the com mand and places the value at the new address on Ports 3 and 4 For example when the slave re...

Страница 96: ...me Programming The 87C196KB can program itself under software con trol One byte or word can be programmed instead of the entire array The only additional requirement is that you apply a programming vo...

Страница 97: ...gram counter an instruc tion after address 3FFAH may not access protected memory Also note the interrupt vectors and CCB are not read protected EA is latched on reset so the device cannot be switched...

Страница 98: ...lculat ed by using the following equation Voltage e 20 256 test ROM data The values for the signature word and voltage levels are shown in Figure 16 10 Description Location Value Signature Word 2070H...

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