80C196KB USER’S GUIDE
Serial Port Interrupts
The serial port generates one of three possible inter-
rupts: Transmit interrupt TI(2030H), Receive Interrupt
RI(2032H) and SERIAL(200CH). Refer to section 10
for information on the serial port interrupts. The
8096BH shared the TI and RI interrupts on the SERI-
AL interrupt vector. On the 80C196KB, these inter-
rupts share both the serial interrupt vector and have
their own interrupt vectors. Ideally, the transmit and
receive interrupts should be programmed as separate
interrupt vectors while disabling the SERIAL inter-
rupt. For 8096BH compatibility, the interrupts can still
use the SERIAL interrupt vector.
HSI FIFO FULL and HSI DATA AVAILABLE
HSI FIFO FULL and HSI DATA AVAILABLE in-
terrupts shared the HSI DATA AVAILABLE inter-
rupt vector on the 8096BH. The source of the HSI
DATA AVAILABLE interrupt is controlled by the
setting of I/O Control Register 1,(IOC1.7). Setting
IOC1.7 to zero will generate an interrupt when a time
value is loaded into the holding register. Setting the bit
to one generates an interrupt when the FIFO, indepen-
dent of the holding register, has six entries in it.
On the 80C196KB, separate interrupt vectors are avail-
able for the HSI FIFO FULL(203CH) and HSI DATA
AVAILABLE(2004H)
interrupts.
The
interrupts
should be programmed for separate interrupt vector lo-
cations. Refer to Section 8 for more information on the
High Speed Inputs.
HSI FIFOÐ4
The HSI FIFO can generate an interrupt when the HSI
has four or more entries in the FIFO. The HSI FIFOÐ
4 interrupt vectors through location 2034H. Refer to
Section 8 for more information on the High Speed In-
puts.
HSI.0 External Interrupt
The rising edge on HSI.0 pin can be used as an external
interrupt. The HSI.0 pin is sampled during PH1 or
CLKOUT low. Sampling is guaranteed if the pin is
held for at least one state time. The interrupt vectors
through location 2008H. The pin does not need to be
enabled to the HSI FIFO in order to generate the inter-
rupt.
Timer2 and Timer1 overflow
Timer2 and Timer1 can interrupt on overflow. These
interrupts shared the same interrupt vector TIMER
OVERFLOW(2000H) on the 8096BH. The interrupts
are individually enabled by setting bits 2 and 3 of IOC1:
bit 2 for Timer1, and bit 3 for Timer2. Which timer
actually caused the interrupt can be determined by bits
4 and 5 of IOS1: bit 4 for Timer2 and 5 for Timer1. On
the 80C196KB Timer2 overflow(0H or 8000H) has a
separate interrupt vector through location 2038H.
Timer2 Capture
The 80C196KB can generate an interrupt in response
to a Timer2 capture triggered by a rising edge on P2.7.
Timer2 Capture vectors through location 2036H.
High Speed Outputs
The High Speed Outputs interrupt can be generated in
response to a programmed HSO command which caus-
es an external event. HSO commands which set or clear
the High Speed Output pins are considered external
events. Status Register IOS2 indicates which HSO
events have occured and can be used to arbitrate which
HSO command caused the interrupt. The High Speed
Output interrupt vectors indirectly through location
2006H. For more information on High Speed Outputs,
refer to Section 9.
Software Timers
HSO commands which create internal events can inter-
rupt through the Software Timer interrupt vector. In-
ternal events include triggering an A/D conversion, re-
setting Timer2 and software timers. Status registers
IOS2 and IOS1 can be used to determine which internal
HSO event has occured. Location 200AH is the inter-
rupt vector for the Software Timer interrupt. Refer to
Section 9 for more information on software timers and
the HSO.
A/D Conversion Complete
The A/D Conversion Complete interrupt can generate
an interrupt in response to a completed A/D conver-
sion. The interrupt vectors indirectly through location
2002H. Refer to section 11 for more information on the
A/D Converter.
6.0 Pulse Width Modulation Output
(D/A)
Digital to analog conversion can be done with the Pulse
Width Modulation output; a block diagram of the cir-
cuit is shown in Figure 6-1. The 8-bit counter is incre-
mented every state time. When it equals 0, the PWM
output is set to a one. When the counter matches the
value in the PWM register, the output is switched low.
When the counter overflows, the output is once again
switched high. A typical output waveform is shown in
33
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Содержание 80C196KB Series
Страница 1: ...November 1990 80C196KB User s Guide Order Number 270651 003 http www agreenleaf cn...
Страница 59: ...80C196KB USER S GUIDE Figure 11 7 Ideal A D Characteristic 270651 37 55 http www agreenleaf cn...
Страница 60: ...80C196KB USER S GUIDE Figure 11 8 Actual and Ideal Characteristics 270651 38 56 http www agreenleaf cn...
Страница 61: ...80C196KB USER S GUIDE Figure 11 9 Terminal Based Characteristic 270651 39 57 http www agreenleaf cn...
Страница 70: ...80C196KB USER S GUIDE Figure 13 5 Reset Sequence 80C196KB Reset Sequence 270651 45 66 http www agreenleaf cn...
Страница 83: ...80C196KB USER S GUIDE 270651 80 Figure 15 14 AC Timing Diagrams 79 http www agreenleaf cn...
Страница 84: ...80C196KB USER S GUIDE 270651 81 270651 84 Figure 15 14 AC Timing Diagrams Continued 80 http www agreenleaf cn...