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80C196KB USER’S GUIDE

5.1 Interrupt Control

Interrupt Pending Register

When the hardware detects one of the sixteen inter-
rupts it sets the corresponding bit in one of two pending
interrupt registers (INTÐPEND-09H and INTÐ

PEND1-12H). When the interrupt vector is taken, the
pending bit is cleared. These registers, the formats of
which are shown in Figure 5-3, can be read or modified
as byte registers. They can be read to determine which
of the interrupts are pending at any given time or modi-
fied to either clear pending interrupts or generate inter-
rupts under software control. Any software which
modifies the INTÐPEND registers should ensure that

the entire operation is inseparable. The easiest way to
do this is to use the logical instructions in the two or
three operand format, for example:

ANDB

INT PEND,

11111101B

; Clears the A/D Interrupt

ORB

INT PEND,

00000010B

; Sets the A/D Interrupt

Caution must be used when writing to the pending reg-
ister to clear interrupts. If the interrupt has already
been acknowledged when the bit is cleared, a 5 state
time ‘‘partial’’ interrupt cycle will occur. This is be-
cause the 80C196KB will have to fetch the next instruc-
tion of the normal instruction flow, instead of proceed-
ing with the interrupt processing. The effect on the pro-
gram will be essentially that of an extra two NOPs.
This can be prevented by clearing the bits using a 2
operand immediate logical, as the 80C196KB holds off
acknowledging interrupts during these ‘‘read/modify/
write’’ instructions.

Interrupt Mask Register

Individual interrupts can be enabled or disabled by set-
ting or clearing bits in the interrupt mask registers
(INTÐMASK-08H and INTÐMASK1-13H). The

format of these registers is the same as that of the Inter-
rupt Pending Register shown in Figure 5-3.

The INTÐMASK and INTÐMASK1 registers can be

read or written as byte registers. A one in any bit posi-
tion will enable the corresponding interrupt source and
a zero will disable the source. The hardware will save
any interrupts that occur by setting bits in the pending
register, even if the interrupt mask bit is cleared. The
INTÐMASK register is the lower eight bits of the

PSW so the PUSHF and POPF instructions save and
restore the INTÐMASK register as well as the global

interrupt lockout and the arithmetic flags. Both the
INTÐMASK and INTÐMASK1 registers can be

saved with the PUSHA and POPA Instructions.

Global Disable

The processing of all interrupts except the NMI, TRAP
and unimplemented opcode interrupts can be disabled
by clearing the I bit in the PSW. Setting the I bit will
enable interrupts that have mask register bits which are
set. The I bit is controlled by the EI (Enable Interrupts)
and DI (Disable Interrupts) instructions. Note that the
I bit only controls the actual servicing of interrupts.
Interrupts that occur during periods of lockout will be
held in the pending register and serviced on a priori-
tized basis when the lockout period ends.

5.2 Interrupt Priorities

The priority encoder looks at all of the interrupts which
are both pending and enabled, and selects the one with
the highest priority. The priorities are shown in Figure
5-4 (15 is highest, 0 is lowest). The interrupt generator
then forces a call to the location in the indicated vector
location. This location would be the starting location of
the Interrupt Service Routine (ISR).