Intel 80C196KB Series, Руководство пользователя, Страница: 44 / 98

80C196KB USER’S GUIDE
If the HSIÐTIME register is read without the holding
register being loaded, the returned value will be indeter-
minate. Under the same conditions, the four bits in
HSIÐSTATUS indicating which events have occurred
will also be indeterminate. The four HSIÐSTATUS
bits which indicate the current state of the pins will
always return the correct value.
It should be noted that many of the Status register con-
ditions are changed by a reset, see section 13. Writing
to HSIÐTIME in window 15 will write to the HSI
FIFO holding register. Writing to HSIÐSTATUS in
Window 15 will set the status bits but will not affect the
input bits.
8.3 HSI Interrupts
Interrupts can be generated by the HSI unit in three
ways: when a value moves from the FIFO into the
holding register; when the FIFO (independent of the
holding register) has 4 or more event stored; when the
FIFO has 6 or more events.
The HSI DATA AVAILABLE and HSI FIFO FULL
interrupts are shared on the 8096BH. The source for
the HSI DATA AVAILABLE interrupt is controlled
by IOC1.7. When IOC1.7 is cleared, the HSI will gen-
erate an interrupt when the holding register is loaded.
The interrupt indicates at least one HSI event has oc-
curred and is ready to be processed. The interrupt vec-
tors through location 2004H. The interrupt is enabled
by setting INTÐMASK.2. The generation of a HSI
DATA AVAILABLE interrupt will set IOS1.7. The
HSI FIFO FULL interrupt will vector through HSI
DATA AVAILABLE if IOC1.7 is set. On the
80C196KB, the HSI FIFO FULL has a separate inter-
rupt vector at location 203CH.
A HSI FIFO FULL interrupt occurs when the HSI
FIFO has six or more entries loaded independent of the
holding register. Since all interrupts are rising edge trig-
gered, the processor will not be reinterrupted until the
FIFO first contains 5 or less records, then contains six
or more. The HSI FIFO FULL interrupt mask bit is
INTÐMASK1.6. The occurrence of a HSI FIFO
FULL interrupt is indicated by IOS1.6. Earlier warning
of a impending FIFO full condition can be achieved by
the HSI FIFO 4th Entry interrupt.
The HSIÐFIFOÐ4 interrupt generates an interrupt
when four or more events are stored in the HSI FIFO
independent of the holding register. The interrupt is
enabled by setting INTÐMASK1.2. The HSIÐ
FIFOÐ4 vectors indirectly through location 2034H.
There is no status flag associated with the HSIÐ
FIFOÐ4 interrupt since it has its own independent in-
terrupt vector.
The HSI.0 pin can generate an interrupt on the rising
edge even if its not enabled to the HSI FIFO. An inter-
rupt generated by this pin vectors through location
2008H.
8.4 HSI Input Sampling
The HSI pins are sampled internally once each state
time. Any value on these pins must remain stable for at
least 1 full state time to guarantee that it is recognized.
The actual sampling occurs during PH1 or during
CLKOUT low. The HSI inputs should be valid at least
30 nsec before the rising of CLKOUT. Otherwise, the
HSI input may be sampled in the next CLKOUT.
Therefore, if information is to be synchronized to the
HSI it should be latched on the rising edge of
CLKOUT.
8.5 Initializing the HSI
To start the HSI, the following steps and the sequence
must be observed; 1) flush the FIFO, 2) enable the HSI
interrupts, and 3) initialize and enable the HSI pins.
The following section of code can be used to flush the
FIFO:
reflush: ld 0, HSI TIME ;clear an event
skip0 ;wait 8 state times
skip0
jbs IOS1, 7, reflush
Enabling the HSI pins before enabling the interrupts
can cause a FIFO lockout condition. For example, if
the HSI pins were enabled first, an event could get
loaded into the holding register before the HSIÐ
DATAÐAVAILABLE interrupt is enabled. If this
happens, no HSIÐDATAÐAVAILABLE interrupts
will ever occur.
9.0 HIGH SPEED OUTPUTS
The High Speed Output unit (HSO) trigger events at
specific times with minimal CPU overhead. Events are
generated by writing commands to the HSOÐCOM-
MAND register and the relative time at which the
events are to occur into the HSOÐTIME register. In
Window 15, these registers will read the last value pro-
grammed in the holding register. The programmable
events include: starting an A/D conversion, resetting
Timer2, setting 4 software flags, and switching 6 output
lines (HSO.0 through HSO.5). The format of the
HSOÐCOMMAND register is shown in Figure 9-1.
Commands 0CH and 0DH are reserved for use on fu-
ture products. Up to eight events can be pending at one
time and interrupts can be generated whenever any of
these events are triggered. HSO.4 and HSO.5 are bi-
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