Intel 80C196KB Series, Руководство пользователя, Страница: 52 / 98

80C196KB USER’S GUIDE
The Transmitter Empty (TXE) bit is set if the transmit
buffer is empty and ready to take up to two characters.
TXE gets cleared as soon as a byte is written to SBUF.
Two bytes may be written consecutively to SBUF if
TXE is set. One byte may be written if TI alone is set.
By definition, if TXE has just been set, a transmission
has completed and TI will be set. The TI bit is reset
when the CPU reads the SPÐSTAT registers.
The TB8 bit is cleared after each transmission and both
TI and RI are cleared when SPÐSTAT read. The RI
and TI status bits can be set by writing to SPÐSTAT in
window 15 but they will not cause an interrupt. Read-
ing of SPÐCON in Window 15 will read the last value
written. Whenever the TXD pin is used for the serial
port it must be enabled by setting IOC1.5 to a 1. I/O
control register 1 can be read in window 15 to deter-
mine the setting.
STARTING TRANSMISSIONS AND RECEPTIONS
In Mode 0, if REN
e
0, writing to SBUF (TX) will
start a transmission. Causing a rising edge on REN, or
clearing RI with REN
e
1, will start a reception. Set-
ting REN
e
0 will stop a reception in progress and
inhibit further receptions. To avoid a partial or com-
plete undesired reception, REN must be set to zero be-
fore RI is cleared. This can be handled in an interrupt
environment by using software flags or in straight-line
code by using the Interrupt Pending register to signal
the completion of a reception.
In the asynchronous modes, writing to SBUF (TX)
starts a transmission. A falling edge on RXD will begin
a reception if REN is set to 1. New data placed in
SBUF (TX) is held and will not be transmitted until the
end of the stop bit has been sent.
In all modes, the RI flag is set after the last data bit is
sampled approximately in the middle of the bit time.
Also for all modes, the TI flag is set after the last data
bit (either 8
th
or 9
th
) is sent, also in the middle of the
bit time. The flags clear when SPÐSTAT is read, but
do not have to be clear for the port to receive or trans-
mit. The serial port interrupt bit is set as a logical OR
of the RI and TI bits. Note that changing modes will
reset the Serial Port and abort any transmission or re-
ception in progress on the channel.
BAUD RATES
Baud rates are generated based on either the T2CLK
pin or XTAL1 pin. The values used are different than
those used for the 8096BH because the 80C196KB uses
a divide-by-2 clock instead of a divide-by-3 clock to
generate the internal timings. Baud rates are calculated
using the following formulas where BAUDÐREG is
the value loaded into the baud rate register:
Asynchronous Modes 1, 2 and 3:
BAUDÐREG
e
XTAL1
Baud Rate * 16
b
1 OR
T2CLK
Baud Rate * 8
Synchronous Mode 0:
BAUDÐREG
e
XTAL1
Baud Rate * 2
b
1 OR
T2CLK
Baud Rate
The most significant bit in the baud register value is set
to a one to select XTAL1 as the source. If it is a zero
the T2CLK pin becomes the source. The following ta-
ble shows some typical baud rate values.
BAUD RATES AND BAUD REGISTER VALUES
Baud XTAL1 Frequency
Rate
8.0 MHz 10.0 MHz 12.0 MHz
300 1666 /
b
0.02 2082 / 0.02 2499 / 0.00
1200 416 /
b
0.08 520 /
b
0.03 624 / 0.00
2400 207 / 0.16 259 / 0.16 312 /
b
0.16
4800 103 / 0.16 129 / 0.16 155 / 0.16
9600 51 / 0.16 64 / 0.16 77 / 0.16
19.2K 25 / 0.16 32 / 1.40 38 / 0.16
Baud Register Value / % Error
A maximum baud rate of 750 Kbaud is available in the
asynchronous modes with 12 MHz on XTAL1. The
synchronous mode has a maximum rate of 3.0 Mbaud
with a 12 MHz clock. Location 0EH is the Baud Regis-
ter. It is loaded sequentially in two bytes, with the low
byte being loaded first. This register may not be loaded
with zero in serial port Mode 0.
48
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1249/0.00
600
89C3
84E1
8270
8138
804D
809B
8026
XTAL1
时16进
制值