Intel 80C196KB Series, Руководство пользователя, Страница: 76 / 98

80C196KB USER’S GUIDE
CLKOUT drives ALE inactive. The next falling edge
of CLKOUT asserts RD (read) and floats the bus for a
read cycle. During a WR (write) cycle, this edge asserts
WR and drives valid data on the bus. On the last rising
edge of CLKOUT, data is latched into the 80C196KB
for a read cycle, or data is valid for a write cycle.
READY Pin
The READY pin can insert wait states into the bus
cycle for interfacing to slow memory or peripherals. A
wait state is 2 Tosc in length. Since the bus is synchro-
nized to CLKOUT, it can only be held for an integral
number of waitstates. Because the 80C196KB is a com-
pletely static part, the number of waitstates that can be
inserted into a bus cycle is unbounded. Refer to the
next section for information on internally controlling
the number of waitstates inserted into a bus cycle.
There are several setup and hold times associated with
the READY signal. If these timings are not met, the
part may insert the incorrect number of waitstates.
INST Pin
The INST pin is useful for decoding more than 64K of
addressing space. The INST pin allows both 64K of
code space and 64K of data space. For instruction
fetches from external memory, the INST pin is assert-
ed, or high for the entire bus cycle. For data reads and
writes, the INST pin is low. The INST pin is low for
the Chip Configuration Byte fetch and for interrupt
vector fetches.
15.2 Chip Configuration Register
The CCR (Chip Configuration Register) is the first
byte fetched from memory following a chip reset. The
CCR is fetched from the CCB (Chip Configuration
Byte) at location 2018H in either internal or external
memory depending on the state of the EA pin. The
CCR is only written once during the reset sequence.
Once loaded, the CCR cannot be changed until the next
reset.
The CCR is shown in Figure 15-2. The two most signif-
icant bits control the level of ROM/EPROM protec-
tion. ROM/EPROM protection is covered in the last
section. The next two bits control the internal READY
mode. The next three bits determine the bus control
signals. The last bit enables or disables the Powerdown
Mode. Before the CCB fetch, if the program memory is
external, the CPU assumes that the bus is configured as
an 8-bit bus. In the 8-bit bus mode, during the CCB
fetch, address lines 8 – 15 use only the weak drivers.
However, in a 16-bit bus system, the external memory
device will be driving the high byte of the bus while
outputting the CCB. This could cause bus contention if
location 2019H contains FFH. A value 20H in location
2019H will help prevent the contention.
270651 – 51
Figure 15-2. Chip Configuration Register
READY control
To simplify ready control, four modes of internal ready
control are available. The modes are chosen by bits 4
and 5 of the CCR and are shown in Figure 15-3.
IRC1 IRC0 Description
0 0 Limit to one wait state
0 1 Limit to two wait states
1 0 Limit to three wait states
1 1 Wait states not limited internally
Figure 15-3. Ready Control Modes
The internal ready control logic limits the number of
waitstates that slow devices can insert into the bus cy-
cle. When the READY pin is pulled low, waitstates are
inserted into the bus cycle until the READY pin goes
high, or the number of waitstate equal the number pro-
grammed into the CCR. So the ready control is a sim-
ple logical OR between the READY pin and the inter-
nal ready control.
72
数控原理与维修
http://www.agreenleaf.cn
11001011