80C196KB USER’S GUIDE
When this procedure is entered at run time the stack
will contain the parameters in the following order:
?????? : param1
high word of param2
low word of param2
param3
return address
w
StackÐpointer
Figure 3-5. Stack Image
If a procedure returns a value to the calling code (as
opposed to modifying more global variables) then the
result is returned in the variable PLMREG. PLMREG
is viewed as either an 8-, 16- or 32-bit variable depend-
ing on the type of the procedure.
The standard calling convention adopted by PLM-96
has several key features:
a) Procedures can always assume that the eight bytes of
register file memory starting at PLMREG can be
used as temporaries within the body of the proce-
dure.
b) Code which calls a procedure must assume that the
eight bytes of register file memory starting at
PLMREG are modified by the procedure.
c) The Program Status Word (PSWÐsee Section 3.3) is
not saved and restored by procedures so the calling
code must assume that the condition flags (Z, N, V,
VT, C, and ST) are modified by the procedure.
d) Function results from procedures are always re-
turned in the variable PLMREG.
PLM-96 allows the definition of INTERRUPT proce-
dures which are executed when a predefined interrupt
occurs. These procedures do not conform to the rules of
a normal procedure. Parameters cannot be passed to
these procedures and they cannot return results. Since
they can execute essentially at any time (hence the term
interrupt), these procedures must save the PSW and
PLMREG when they are entered and restore these val-
ues before they exit.
3.7 Software Protection Hints
Several features to assist in recovery from hardware
and software errors are available on the 80C196KB.
Protection is also provided against executing unimple-
mented opcodes by the unimplemented opcode inter-
rupt. In addition, the hardware reset instruction (RST)
can cause a reset if the program counter goes out of
bounds. This instruction has an opcode of 0FFH, so if
the processor reads in bus lines which have been pulled
high it will reset itself.
It is recommended that unused areas of code be filled
with NOPs and periodic jumps to an error routine or
RST (reset chip) instructions. This is particularly im-
portant in the code around lookup tables, since if look-
up tables are executed undesired results will occur.
Wherever space allows, each table should be surround-
ed by 7 NOPs (the longest 80C196KB instruction has 7
bytes) and a RST or jump to error routine instruction.
Since RST is a one-byte instruction, the NOPs are not
needed if RSTs are used instead of jumps to an error
routine. This will help to ensure a speedy recovery
should the processor have a glitch in the program flow.
The Watchdog Timer (WDT) further protects against
software and hardware errors. When using the WDT to
protect software it is desirable to reset it from only one
place in code, lessening the chance of an undesired
WDT reset. The section of code that resets the WDT
should monitor the other code sections for proper oper-
ation. This can be done by checking variables to make
sure they are within reasonable values. Simply using a
software timer to reset the WDT every 10 milliseconds
will provide protection only for catastrophic failures.
4.0 PERIPHERAL OVERVIEW
There are five major peripherals on the 80C196KB: the
pulse-width-modulated output (PWM), Timer1 and
Timer2, High Speed I/O Unit, Serial Port and A/D
Converter. With the exception of the high speed I/O
unit (HSIO), each of the peripherals is a single unit that
can be discussed without further separation.
Four individual sections make up the HSIO and work
together to form a very flexible timer/counter based
I/O system. Included in the HSIO are a 16-bit timer
(Timer1), a 16-bit up/down counter (Timer2), a pro-
grammable high speed input unit (HSI), and a pro-
grammable high speed output unit (HSO). With very
little CPU overhead the HSIO can measure pulse
widths, generate waveforms, and create periodic inter-
rupts. Depending on the application, it can perform the
work of up to 18 timer/counters and capture/compare
registers.
A brief description of the peripheral functions and in-
terractions is included in this section. It provides over-
view information prior to the detailed discussions in the
following sections. All of the details on control bits and
precautions are in the individual sections for each pe-
ripheral starting with Section 5.
23
数控原理与维修
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Содержание 80C196KB Series
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Страница 59: ...80C196KB USER S GUIDE Figure 11 7 Ideal A D Characteristic 270651 37 55 http www agreenleaf cn...
Страница 60: ...80C196KB USER S GUIDE Figure 11 8 Actual and Ideal Characteristics 270651 38 56 http www agreenleaf cn...
Страница 61: ...80C196KB USER S GUIDE Figure 11 9 Terminal Based Characteristic 270651 39 57 http www agreenleaf cn...
Страница 70: ...80C196KB USER S GUIDE Figure 13 5 Reset Sequence 80C196KB Reset Sequence 270651 45 66 http www agreenleaf cn...
Страница 83: ...80C196KB USER S GUIDE 270651 80 Figure 15 14 AC Timing Diagrams 79 http www agreenleaf cn...
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