Intel 80C196KB Series, Руководство пользователя, Страница: 74 / 98

80C196KB USER’S GUIDE
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Figure 14-1. Power Up and Power Down Sequence
In Powerdown, the bus control pins go to their inactive
states. All of the output pins will assume the value in
their data latches. Ports 3 and 4 will continue to act as
ports in the single chip mode or will float if acting as
the ADDR/DATA bus.
To prevent accidental entry into the Powerdown Mode,
this feature may be disabled at reset by clearing bit 0 of
the CCR (Chip Configuration Register). Since the de-
fault value of the CCR bit 0 is 1, the Powerdown Mode
is normally enabled.
The Powerdown Mode can be exited by a chip reset or
a high level on the external interrupt pin. If the RESET
pin is used, it must be asserted long enough for the
oscillator to stabilize.
When exiting Powerdown with an external interrupt, a
positive level on the pin mapped to INT7 (either
EXTINT or port0.7) will bring the chip out of Power-
down Mode. The interrupt does not have to be un-
masked to exit Powerdown. An internal timing circuit
ensures that the oscillator has time to stabilize before
turning on the internal clocks. Figure 14-1 shows the
power down and power up sequence using an external
interrupt.
During normal operation, before entering Powerdown
Mode, the V
PP
pin will rise to V
CC
through an internal
pullup. The user must connect a capacitor between V
PP
and V
SS
. A positive level on the external interrupt pin
starts to discharge this capacitor. The internal current
source that discharges the capacitor can sink approxi-
mately 100 uA. When the voltage goes below about 1
volt on the V
PP
pin, the chip begins executing code. A
1uF capacitor would take about 4 ms to discharge to 1
volt.
If the external interrupt brings the chip out of Power-
down, the corresponding bit will be set in the interrupt
pending register. If the interrupt is unmasked, the part
will immediately execute the interrupt service routine,
and return to the instruction following the IDLPD in-
struction that put the chip into Powerdown. If the in-
terrupt is masked, the chip will start at the instruction
following the IDLPD instruction. The bit in the pend-
ing register will remain set, however.
All peripherals should be in an inactive state before
entering Powerdown. If the A/D converter is in the
middle of a conversion, it is aborted. If the chip comes
out of Powerdown by an external interrupt, the serial
port will continue where it left off. Make sure that the
serial port is done transmitting or receiving before en-
tering Powerdown. The SFRs associated with the A/D
and the serial port may also contain incorrect informa-
tion when returning from Powerdown.
When the chip is in Powerdown, it is impossible for the
watchdog timer to time out because its clock has
stopped. Systems which must use the Watchdog and
Powerdown, should clear the Watchdog right before
entering Powerdown. This will keep the Watchdog
from timing out when the oscillator is stabilizing after
leaving Powerdown.
14.3 ONCE and Test Modes
Test Modes can be entered on the 80C196KB by hold-
ing ALE, INST or RD in their active state on the rising
edge of RESET. The only Test Mode not reserved for
use by Intel is the ONCE, or ON-Circuit-Emulation
Mode.
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数控原理与维修
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